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WM8961GEFL/V Datasheet(PDF) 68 Page - Wolfson Microelectronics plc |
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WM8961GEFL/V Datasheet(HTML) 68 Page - Wolfson Microelectronics plc |
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68 / 116 page  WM8961 Pre-Production w PP, August 2009, Rev 3.1 68 WSEQ _LOCATION WM8961 REG _INDEX EOS WIDTH START DATA DELAY COMMENT CUMULATIVE DELAY STARTUP TIME 30 8’h45 1’b0 3’h4 4’h3 8’h0E 4’h0 Clear RMV_SHRT on outputs 0.0005 0.0180 31 8’h45 1’b0 3’h4 4’h2 8’h0C 4’h0 Clear HPL_ENA_OUTP & HPR_ENA_OUTP 0.0005 0.0185 32 8’h02 1’b0 3’h6 4’h0 8’h00 4’h0 LOUTVOL to mute 0.0005 0.0190 33 8’h03 1’b0 3’h6 4’h0 8’h00 4’h0 ROUTVOL to mute 0.0005 0.0195 34 8’h03 1’b0 3’h0 4’h8 8’h01 4’h0 OUT1VU 0.0005 0.0200 35 8’h28 1’b0 3’h6 4’h0 8’h00 4’h0 SPKLVOL to mute 0.0005 0.0205 36 8’h29 1’b0 3’h6 4’h0 8’h00 4’h0 SPKRVOL to mute 0.0005 0.0210 37 8’h29 1’b0 3’h0 4’h8 8’h01 4’h0 SPKVU 0.0005 0.0215 38 8’h3C 1’b0 3’h4 4’h3 8’h00 4’h0 Disable Servo on inputs 0.0005 0.0220 39 8’h3D 1’b0 3’h4 4’h3 8’h00 4’h0 Disable Servo on outputs 0.0005 0.0225 40 8’h1A 1’b0 3’h5 4’h3 8’h00 4’h0 SPKL_PGA = 0, SPKR_PGA = 0, LOUT1_PGA = 0, ROUT1_PGA = 0, DACL = 0, DACR = 0 0.0005 0.0230 41 8’h31 1’b0 3’h1 4’h6 8’h00 4’h0 Disable Class D 0.0005 0.0235 42 8’h45 1’b0 3’h5 4’h0 8’h00 4’h0 Disable HPL_ENA, HPR_ENA, HPL_ENA_DLY, HPR_ENA_DLY 0.0005 0.0240 43 8’h48 1’b0 3’h0 4’h0 8’h00 4’h0 Disable Charge Pump 0.0005 0.0245 44 8’h19 1’b0 3’h5 4’h1 8’h00 4’h0 VREF = 0 ; ADCL = 0 ; ADCR = 0 ; MICB = 0 ; AINL = 0 ; AINR = 0 0.0005 0.0250 45 8’h1C 1’b0 3’h1 4’h3 8’h00 4’h0 BUFDCOPEN = 0, BUFIOEN = 0 ; Disable current bias circuits 0.0005 0.0255 46 8’h19 1’b0 3’h1 4’h7 8’h00 4’h0 VMIDSEL = 00, disable VMID 0.0005 0.0260 47 8’h08 1’b0 3’h0 4’h4 8’h00 4’h0 CLK_DSP_ENA = 0 0.0005 0.0265 48 8’hFE 1’b1 3’h0 4’h0 8’h00 4’h0 Dummy Write for expansion 0.0005 0.0270 Table 50 Write Sequencer Default Values (RAM =Locations 0-31, ROM = Locations 32-48) |
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