PIC24FJ128GA310 datasheet(161/406 Pages) MICROCHIP

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DS39996F-page 161

PIC24FJ128GA310 FAMILY

When the RTCC is enabled, it continues to operate with

the same clock source (SOSC or LPRC) that was

selected prior to entering VBAT mode. There is no pro-

vision to switch to a lower power clock source after the

mode switch.

Since the loss of VDD is usually an unforeseen event, it

is recommended that the contents of the Deep Sleep

Semaphore registers be loaded with the data to be

retained at an early point in code execution.

10.5.1

VBAT MODE WITH NO RTCC

By disabling RTCC operation during VBAT mode, power

consumption is reduced to the lowest of all

power-saving modes. In this mode, only the Deep

Sleep Semaphore registers are maintained.

10.5.2

WAKE-UP FROM VBAT MODES

When VDD is restored to a device in VBAT mode, it auto-

matically wakes. Wake-up occurs with a POR, after

which the device starts executing code from the Reset

vector. All SFRs, except the Deep Sleep Semaphores

and RTCC registers are reset to their POR values. If

the RTCC was not configured to run during VBAT mode,

it will remain disabled and RTCC will not run. Wake-up

timing is similar to that for a normal POR.

To differentiate a wake-up from VBAT mode from other

POR states, check the VBAT status bit (RCON2<0>). If

this bit is set while the device is starting to execute the

code from Reset vector, it indicates that there has been

an exit from VBAT mode. The application must clear the

VBAT bit to ensure that future VBAT wake-up events are

captured.

If a POR occurs without a power source connected to

the VBAT pin, the VBPOR bit (RCON2<1>) is set. If this

bit is set on a POR, it indicates that a battery needs to

be connected to the VBAT pin.

In addition, if the VBAT power source falls below the

level needed for Deep Sleep Semaphore operation

while in VBAT mode (e.g., the battery has been

drained), the VBPOR bit will be set. VBPOR is also set

when the microcontroller is powered up the very first

time, even if power is supplied to VBAT.

With VBPOR set, the user should clear it, and the next

time, this bit will only set when VDD = 0 and the VBAT

pin has gone below level (0.4V-0.6V).

10.5.3

I/O PINS DURING VBAT MODES

All I/O pins should be maintained at VSS level; no I/O

pins should be given VDD (refer to “Absolute Maximum

Ratings”

) during VBAT mode. The only exceptions are

the SOSCI and SOSCO pins, which maintain their states

if the secondary oscillator is being used as the RTCC

clock source. It is the user’s responsibility to restore the

I/O pins to their proper states, using the TRIS and LAT

bits, once VDD has been restored.

10.5.4

SAVING CONTEXT DATA WITH THE

DSGPRn REGISTERS

As with Deep Sleep mode, all SFRs are reset to their

POR values after VDD has been restored. Only the

Deep Sleep Semaphore registers are preserved. Appli-

cations which require critical data to be saved should

save it in DSGPR0 and DSGPR1.

The BOR should be enabled for the reliable operation

of the VBAT.

Note:

If the VBAT mode is not used, the

recommendation is to connect the VBAT

pin to VDD.

When the VBAT mode is used (connected

to the battery), as well as when it is not

used, it is always recommended to

connect a 0.1 µF capacitor from the VBAT

pin to ground. The capacitor should be

located very close to the VBAT pin.

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