HMC833LP6GE datasheet(39/61 Pages) HITTITE

39 / 61 page

For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824

Phone: 978-250-3343

Fax: 978-250-3373

Order On-line at www.hittite.com

Application Support: Phone: 978-250-3343 or apps@hittite.com

HMC833LP6GE

v01.1012

FRACTIONAL-N PLL WITH INTEGRATED VCO

25 - 6000 MHz

and to decide which data to export from the chip.

In its default configuration, after power-on-reset, the output driver is disabled, and only drives during

appropriately addressed SPI reads. This allows it to share the output with other devices on the same bus.

Depending on the SPI mode, the read section of SPI cycle is recognized differently

HMC SPI Mode: The driver is enabled during the last 24 bits of SPI READ cycle (not during write

cycles).

Open SPI Mode: The driver is enabled if the chip is addressed - ie. The last 3 bits of SPI cycle =

‘000’b before the rising edge of SEN (Note A).

To monitor any of the GPO signals, including Lock Detect, set Reg 0Fh[7] = 1 to keep the SDO driver

always on. This stops the LDO driver from tri-stating and means that the SDO line cannot be shared with

other devices.

The chip will naturally switch away from the GPO data and export the SDO during an SPI read (Note B). To

prevent this automatic data selection, and always select the GPO signal, set “Prevent AutoMux of SDO”

(Reg 0Fh[6] = 1). The phase noise performance at this output is poor and uncharacterized. Also, the GPO

output should not be toggling during normal operation. Otherwise the spectral performance may degrade.

Note that there are additional controls available, which may be helpful if sharing the bus with other devices:

•

To allow the driver to be active (subject to the conditions above) even when the chip is disabled - set

Reg 01h[7] = 0.

•

To disable the driver completely, set Reg 08h[5] = 0 (it takes precedence over all else).

•

To disable either the pull-up or pull-down sections of the driver, Reg 0Fh[8] = 1 or Reg 0Fh[9] = 1

respectively.

Note A: If SEN rises before SCK has clocked in an ‘invalid’ (non-zero) chip -address, the HMC833LP6GE

will start to drive the bus.

Note B: In Open Mode, the active portion of the read is defined between the 1st SCK rising edge after

SEN, to the next rising edge of SEN.

Example Scenarios:

•

Drive SDO during reads, tri-state otherwise (to allow bus-sharing)

•

No action required.

•

Drive SDO during reads, Lock Detect otherwise

•

Set GPO Select Reg 0Fh[4:0] = ‘00001’ (which is default)

•

Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1)

•

Always drive Lock Detect

•

Set “ Prevent AutoMux of SDO” Reg 0Fh[6] = 1

•

Set GPO Select Reg 0Fh[4:0]= 00001 (which is default)

•

Set “Prevent GPO driver disable” (Reg 0Fh[7] = 1))

The signals available on the GPO are selected by changing “GPO Select”, Reg 0Fh[4:0].

1.17

SERIAL PORT

1.17.1

Serial Port Modes of Operation

The HMC833LP6GE serial port interface can operate in two different modes of operation.

a. HMCSPI HMC Mode (HMC Legacy Mode) - Single slave per HMCSPI Bus

b. HMCSPI Open Mode - Up to 8 slaves per HMCSPI Bus.

Both Modes support 5-bits of register address space. HMC Mode can support up to 6 bits of register

HMC833LP6GE Datasheet(PDF) 39 Page - Hittite Microwave Corporation

HMC833LP6GE Datasheet(HTML) 39 Page - Hittite Microwave Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61

Datasheet Download

Link URL