HMC833LP6GE datasheet(3/61 Pages) HITTITE

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HMC833LP6GE

v01.1012

FRACTIONAL-N PLL WITH INTEGRATED VCO

25 - 6000 MHz

Parameter

Condition

Min.

Typ.

Max.

Units

PLL RF Divider Characteristics

19-Bit N-Divider Range (Integer)

Max = 219 - 1

524,287

19-Bit N-Divider Range (Fractional)

Fractional nominal divide ratio

varies (-3 / +4) dynamically

max

524,283

REF Input Characteristics

Max Ref Input Frequency

350

MHz

Ref Input Voltage

AC Coupled [3]

3.3

Vp-p

Ref Input Capacitance

14-Bit R-Divider Range

16,383

Phase Detector (PD) [4]

PD Frequency Fractional Mode B

[5]

100

MHz

PD Frequency Fractional Mode A (and Regis-

ter 6 [17:16] = 11)

MHz

PD Frequency Integer Mode

125

MHz

Charge Pump

Output Current

0.02

2.54

Charge Pump Gain Step Size

µA

PD/Charge Pump SSB Phase Noise

50 MHz Ref, Input Referred

1 kHz

-143

dBc/Hz

10 kHz

Add 1 dB for Fractional

-150

dBc/Hz

100 kHz

Add 3 dB for Fractional

-153

dBc/Hz

Logic Inputs

Vsw

% DVDD

Logic Outputs

VOH Output High Voltage

DVDD

VOL Output Low Voltage

Output Impedance

100

200

Maximum Load Current

1.5

Power Supply Voltages

3.3 V Supplies

AVDD, VCCHF, VCCPS,

VCCPD, RVDD,DVDD

3.0

3.3

3.5

5 V Supplies

VPPCP, VDDLS, VCC1, VCC2

4.8

5.2

Power Supply Currents

+5 V Analog Charge Pump

VPPCP, VDDCP

+5 V VCO Core and VCO Buffer

fo/1 Mode VCC2

105

fo/N Mode VCC2

+5 V VCO Divider and RF/PLL Buffer

fo/1 Mode VCC1

fo/N Mode VCC1

100

Electrical Specifications (Continued)

[3] Measured with 100 Ω external termination. See “Reference Input Stage” section for more details.

[4] Slew rate of greater or equal to 0.5 ns/V is recommended, see “Reference Input Stage” section for more details. Frequency is guaranteed across

process voltage and temperature from -40 °C to 85 °C.

[5] This maximum phase detector frequency can only be achieved if the minimum N value is respected. eg. In the case of fractional B mode, the

maximum PFD rate = fvco/20 or 100 MHz, whichever is less.

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