AD9789BBCZ datasheet(34/76 Pages) AD

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AD9789

Rev. A | Page 34 of 76

Table 32. Data Control Register (Address 0x21)

Bit

Bit Name

Description

BIN

This bit selects the coding for the device.

0 = twos complement coding.

1 = straight binary coding.

[6:5]

BUSWDTH[1:0]

These bits set the input data bus width for the device.

DATWDTH

Setting

Input Bus Width

4 bits

8 bits

16 bits

This bit sets the data-word width that is sent to the datapaths.

0 = 8-bit data-word.

1 = 16-bit data-word.

CMPLX

This bit configures the datapath for real or complex data.

0 = real data.

1 = complex data.

32 bits

[2:0]

LTNCY[2:0]

These bits set the turnaround latency from the FS pulse to the internal data sampling time. For more information,

see the Latency Register section.

Setting

Latency

000

Input data begins to be sampled at approximately the first rising edge of DCO after FS

goes low.

001

Input data begins to be sampled at approximately the second rising edge of DCO after

FS goes low.

…

111

Input data begins to be sampled at approximately the eighth rising edge of DCO after

FS goes low.

Table 33. DCO Frequency Register (Address 0x22)

Bit

Bit Name

Description

Reserved

Reserved.

[6:4]

DCODIV[2:0]

These bits configure the data clock output (DCO) frequency.

[3:0]

Setting

DCO Clock Frequency

000

DCO clock disabled

001

fDACCLK/16

010

fDACCLK/32

011

Invalid

100

fDACCLK/64

101

Invalid

11x

ONES[3:0]

These bits always read back 1111.

Invalid

AD9789BBCZ Datasheet(PDF) 34 Page - Analog Devices

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