AD9789BBCZ datasheet(37/76 Pages) AD

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AD9789

Rev. A | Page 37 of 76

Table 42. Mu Delay Control 2 Register (Address 0x33)

Bit

Bit Name

Description

MU_CLKDIS

This bit disables or enables the clock to the mu delay controller.

0 = enabled.

1 = disabled.

SLOPE

This bit configures the desired slope for the phase measurement of the mu delay. When the desired phase is

measured, the slope of the phase measurement is calculated and compared to the value of this bit. For optimal

ac performance, the best setting for the search is a positive slope and a phase value of 14.

0 = negative.

1 = positive.

[5:4]

MODE[1:0]

These bits configure the mode of operation for the mu controller.

00 = search and track (recommended).

01 = track only.

10 = search only.

11 = invalid.

MUSAMP

Transitioning this bit from 0 to 1 enables the user to read back the mu delay value that the controller locked to

(the MUDLY bits in Register 0x39 and Register 0x3A), as well as the phase that it locked to (the MUPHZ bits in

0 = no action.

1 = transition from 0 to 1 captures the readback of the mu controller phase and delay.

[2:1]

GAIN[1:0]

These bits set the tracking rate of the mu controller.

00 = slowest tracking.

01 = nominal tracking (recommended).

10 = fastest tracking.

11 = invalid (do not use).

MU_EN

This bit enables or disables the mu controller. Before enabling the mu controller, turn on both the phase

comparator boost (Register 0x3E[5]) and the mu control duty cycle correction circuitry (Register 0x30[7]). Both

of these functions allow for more robust operation of the mu controller over the entire operating speed of the

part.

0 = mu controller off (manual mode).

1 = mu controller on (auto mode).

Table 43. DAC Bias Register (Address 0x36)

Bit

Bit Name

Description

PDBIAS

Setting this bit to 1 powers down the DAC circuitry.

[6:2]

Reserved

Reserved.

[1:0]

MSEL[1:0]

These bits set the mirror roll-off frequency control, which can be used to adjust the noise contribution of the

internal current mirror to optimize the 1/f noise.

00 = bypass the mirror roll-off frequency control.

01 = narrowest bandwidth.

10 = medium bandwidth.

11 = widest bandwidth.

Table 44. DAC Decoder Register (Address 0x38)

Bit

Bit Name

Description

[7:2]

Reserved

Reserved.

[1:0]

DAC decoder

mode

These bits set the decoder mode for the DAC. It is recommended that normal mode (the default) be used.

00 = normal mode.

01 = return to zero mode.

10 = mix mode.

11 = invalid.

AD9789BBCZ Datasheet(PDF) 37 Page - Analog Devices

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