AD9789BBCZ datasheet(43/76 Pages) AD

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AD9789

Rev. A | Page 43 of 76

The calculated FTW for each channel should be entered into

the register locations listed in Table 52.

Table 52. Register Locations of FTWs for Each Channel

FTW

Channel 0

Channel 1

Channel 2

Channel 3

[23:16]

Reg. 0x0C

Reg. 0x0F

Reg. 0x12

Reg. 0x15

[15:8]

Reg. 0x0B

Reg. 0x0E

Reg. 0x11

Reg. 0x14

[7:0]

Reg 0x0A

Reg 0x0D

Reg 0x10

Reg 0x13

The FTW sets the frequency of the sine and cosine signals

generated by the numerically controlled oscillator (NCO).

The complex output from the NCO is multiplied by the input

datapath signal to modulate the signal to the desired output

frequency. A conceptual block diagram of the baseband digital

upconverter is shown in Figure 84.

SIN

COS

FTW NCO FREQUENCY

TUNING WORD

Figure 84. Conceptual Block Diagram of the Baseband Digital Upconverter

Individual Channel Scalar

The last block in the datapath is an 8-bit scalar (Register 0x25 to

hardware roll-offs that may be encountered. The scale factor

applied to each channel is calculated as follows:

128

:0]

CHANxGAIN[

ScaleFacto =

The range of the channel gain is 0 to 1.9921875 with a step size

of 0.0078125. An individual channel can be easily and quickly

muted, if desired, by setting the scale factor to 0.

Table 53. Register Locations for Channel Gain Scalar

CHANxGAIN

Channel 0

Channel 1

Channel 2

Channel 3

[7:0]

Reg. 0x25

Reg. 0x26

Reg. 0x27

Reg. 0x28

The default value of the channel gain provides a scale factor of

1. As shown in Figure 85, the output of the input scalar block is

rounded to the nearest 16-bit value. If the output exceeds the

maximum or minimum value, it is clipped to either positive or

negative full scale (0x7FFF or 0x8000).

ROUND

SATURATE

CHANxGAIN[7:0]

Figure 85. Individual Channel Gain Control

DIGITAL BLOCK UPCONVERTER

The second half of the DSP engine on the AD9789 combines the

outputs of the four datapaths into one block, scales the block of

channels, interpolates by 16× to the full DAC rate, and performs

a band-pass filter operation allowing the block of channels to be

placed anywhere in the Nyquist bandwidth of the DAC.

DATA-

PATH

DATA-

PATH

DATA-

PATH

DATA-

PATH

SUM

SCALE

BPF

DIGITAL BLOCK

UPCONVERTER

BPF

fC = 0 TO

fDAC/2

Figure 86. Functional Block Diagram of the Digital Block Upconverter

Each block of the digital block upconverter is described in more

detail in the following sections.

Summing Junction Scalar

The summing junction scalar block operates on the sum of the

four channels. The value of SUMSCALE[7:0] is programmed in

as follows:

:0]

SUMSCALE[7

ScaleFacto =

This factor provides a scaling range of the input data from 0 to

3.984375 with a step size of 0.015625. The default value of 0x0D

provides a scale factor of 0.203125. Note that when the channels

are summed, they are clipped at the output of the summing

junction scalar block if the value exceeds the maximum or

minimum full-scale value (0x7FFF or 0x8000). If the full 16-bit

range of each individual channel is used, the sum scalar should

be set to 0x10 (0.25) to avoid the possibility of clipping.

ROUND

SATURATE

SUMSCALE

TO SATURATION COUNTER

SATERR

Figure 87. Block Diagram of the Summing Junction Scalar

In practice, the signal-to-noise ratio (SNR) of the channel can

be improved by increasing the sum scale factor and permitting

a small amount of clipping. The larger signal amplitude can

improve the SNR if the clipping is brief and infrequent.

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