PD70F3559 datasheet(42/85 Pages) RENESAS

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R01DS0142ED0100

Data Sheet

Chapter 7

Peripherals specification

7.7.1

MEMC0CLK asynchronous timing

Notes

ASW: Number of Address Setup Wait for multiplex bus

AHW: Number of Address Hold Wait for multiplex bus

w: Number of data wait

In case the bus operational period (T) is shorter then 41ns, tDRDID

requires at least 1 data wait (w=1).

Parameter

Symbol

Condition

Ratings

Unit

Min

Typ

Max

Bus operational period

Address setup time to

MEMC0ASTBZ (f)

tSAST

<1>

(1+ASW)·T-15

Address hold time from

MEMC0ASTBZ (f)

tHSTA

<2>

(1+AHW)·T-15

Address float delay time from

MEMC0RDZ (f)

tFRDA

<3>

Address hold time from

MEMC0RDZ (r)

tHRDA

<4>

Data input delay time from

MEMC0RDZ (f)

tDRDID

<5>

(1+w)·T-35

Data input hold time from

MEMC0RDZ (r)

tHRDID

<6>

Delay time from ASTB(f) to

MEMC0RDZ (f)

tDSTRD

<7>

(1+AHW)·T-15

Delay time from ASTB(f) to

MEMC0WRZ (f)

tDSTWR

<8>

(1+AHW)·T-15

MEMC0RDZ, MEMC0WRZ

low level width

tWRDST

<9>

(1+w)·T-10

Data output delay time from

MEMC0WRZ (f)

tDWROD

<10>

Address hold time from

MEMC0WRZ (r)

tHWRA

<11>

T-15

Data output setup time to

MEMC0WRZ (r)

tSODWR

<12>

(1+w)·T-15

Data output hold time from

MEMC0WRZ (r)

tHWROD

<13>

T-15

MEMC0WAITZ setting delay

from MEMC0ASTBZ (f)

tSSTWT1 <14>

(1+AHW)·T -

(2·HEAPCLK+35)

MEMC0WAITZ hold time from

MEMC0ASTBZ (f)

tSSTWT2 <15> w≥1-

(1+w+AHW)·T -

(2·HEAPCLK+35)

MEMC0WAITZ setting delay

from Address

tHSTWT1 <16> w≥1

(w+AHW)·T-

(2*HEAPCLK+20)

MEMC0WAITZ hold time from

Address

tHSTWT2 <17> w≥1

(1+w+AHW)·T-

2*HEAPCLK+20)

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