 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
PD70F3559 Datasheet(PDF) 61 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
PD70F3559 Datasheet(HTML) 61 Page - Renesas Technology Corp |
|
|
61 / 85 page  61 R01DS0142ED0100 Data Sheet Chapter 7 Peripherals specification 7.12 IIC timing Table 7-7 Normal mode Parameter Symbol Condition Ratings Unit Min Typ Max SCL clock period fCLK 0 100 kHz Bus free time (between stop condition and start condition) tBUF 4.7 - - µs Start/Restart Hold time (New clock pulse is generated after this hold time as a master.) tHD:STA 4 - - µs SCL clock low state hold time tLOW 4.7 - - µs SCL clock high state hold time tHIGH 4 - - µs Setup time for start/restart condition tSU:STA 4.7 - - µs Data hold time tHD:DAT CBUS compatible 5 - - µs IIC bus 0 - - µs Data setup time tSU:DAT 250 - - ns Rising transition time of SDA or SCL tR - - 1000 ns Falling transition time of SDA or SCL tF - - 300 ns Setup time of stop condition tSU:STO 4 - - µs Bus capacitance Cb - - 400 pF |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
