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PD70F3559 Datasheet(PDF) 62 Page - Renesas Technology Corp |
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PD70F3559 Datasheet(HTML) 62 Page - Renesas Technology Corp |
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62 / 85 page ![]() 62 R01DS0142ED0100 Data Sheet Chapter 7 Peripherals specification Table 7-8 Fast mode Notes 1. P: Stop condition Notes 1. S: Start condition Notes 1. Sr: Restart condition Parameter Symbol Condition Ratings Unit Min Typ Max SCL clock period fCLK 0 - 400 kHz Bus free time (between stop condition and start condition) tBUF 1.3 - - µs Start/Restart Hold time (New clock pulse is generated after this hold time as a master.) tHD:STA 0.6 - - µs SCL clock low state hold time tLOW 1.3 - - µs SCL clock high state hold time tHIGH 0.6 - - µs Setup time for start/restart condition tSU:STA 0.6 - - µs Data hold time tHD:DAT IIC bus 0 - 0.9 µs Data setup time tSU:DAT 100 - - ns Rising transition time of SDA or SCL tR 20+0.1Cb - 300 ns Falling transition time of SDA or SCL tF 20+0.1Cb - 300 ns Setup time of stop condition tSU:STO 0.6 - - µs Noise elimination width tSP 0 - 50 ns Bus capacitance Cb - - 400 pF SCL0 P t SU: STA t HD: STA t LOW t HI GH t BUF SDA0 t SP t R t HD: DAT t F t SU: DAT S t HD: STA Sr P t SU: STO |
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