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PD70F3559 Datasheet(PDF) 49 Page - Renesas Technology Corp

Part # PD70F3559
Description  32-bit Single-Chip Microcontroller
PDF  85 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

PD70F3559 Datasheet(HTML) 49 Page - Renesas Technology Corp

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49
R01DS0142ED0100
Data Sheet
Chapter 7
Peripherals specification
(2)
CSIH timing master mode
Table 7-4
CSIH timing (Master mode)
Notes
1.
n: Number of macro instances. Refer to the User Manual for the detailed
specification.
2.
CSSETUP: Value of CSIHnCFG0-7.CSIHnSP0-7[3:0]
3.
CSHOLD: Value of CSIHnCFG0-7.CSIHnHD0-7[3:0]
4.
CSIDLE: Value of CSIHnCFG0-7.CSIHnID0-7[2:0]
Parameter
Symbol
Condition
Ratings
Unit
Min
Typ
Max
Macro Operation clock cycle
time
tKCYHn
20.8
-
-
ns
CSIHnSC cycle time
tKCYMHn
100
-
-
ns
CSIHnSC high level width
tKWHMHn
0.5 · tKCYMHn-10
-
-
ns
CSIHnSC low level width
tKWLMHn
0.5 · tKCYMHn-10
-
-
ns
CSIHnSI setup time
(vs. CSIHnSC )
tSSIMHn
CSIHnSC@PDSC=1
30
-
-
ns
CSIHnSC@PDSC=0
38
-
-
ns
CSIHnSI hold time
(vs. CSIHnSC)
tHSIMHn
0
-
-
ns
CSIHnSO output delay
(vs. CSIHnSC)
tDSOMHn
-
-
7
ns
CSIHnRYI setup time
(vs. CSIHnSC)
tSRYIHn
CSIHnCTL1.CSIHnSIT=x
CSIHnCTL1.CSIHnHSE=1
2 · tKCYHn+25
-
-
ns
CSIHnRYI High level width
tWRYIHn
CSIHnCTL1.CSIHnHSE=1
tKCYHn- 5.0
-
-
ns
CSIHnCSS0-7 inactive
width
tWSCSBHn
CSIDLE ×
tKCYMHn - 5.0
--
ns
CSIHnCSS0-7 setup time
( vs. CSIHnSC )
tSSCSBHn0 CSIHnCTL1.CSIHnDAP=0
CSSETUP ×
tKCYMHn-5.0
--
ns
tSSCSBHn1 CSIHnCTL1.CSIHnDAP=1
(CSSETUP + 0.5 ) ×
tKCYMHn-5.0
--
ns
CSIHnCSS0-7 hold time
( vs. CSIHnSC )
tHSCSBHn0 CSIHnCTL1.CSIHnSIT=0
CSHOLD ×
tKCYMHn-10.0
--
ns
tHSCSBHn1 CSIHnCTL1.CSIHnSIT=1
(CSSHOLD + 0.5) ×
tKCYMHn-5.0
--
ns



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