Chapter 1: Cyclone III Device Datasheet

1–17

Switching Characteristics

July 2012

Altera Corporation

Cyclone III Device Handbook

Volume 2

Table 1–24 lists the active configuration mode specifications for Cyclone III devices.

Table 1–25 lists the JTAG timing parameters and values for Cyclone III devices.

Periphery Performance

This section describes periphery performance, including high-speed I/O, external

memory interface, and IOE programmable delay.

I/O performance supports several system interfacing, for example, the high-speed

I/O interface, external memory interface, and the PCI/PCI-X bus interface. I/O using

the SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM

interfacing speeds with typical DDR SDRAM memory interface setup. I/O using

general-purpose I/O standards such as 3.0-, 2.5-, 1.8-, or 1.5-LVTTL/LVCMOS are

capable of a typical 200 MHz interfacing frequency with a 10 pF load.

HSPICE/IBIS simulations based on your specific design and system setup to

determine the maximum achievable frequency in your system.

Table 1–24. Cyclone III Devices Active Configuration Mode Specifications

Programming Mode

DCLK Range

Unit

Active Parallel (AP)

20 – 40

MHz

Active Serial (AS)

20 – 40

MHz

Table 1–25. Cyclone III Devices JTAG Timing Parameters

(1)

Symbol

Parameter

Min

Max

Unit

TCK clock period

40

—

ns

TCK clock high time

20

—

ns

TCK clock low time

20

—

ns

JTAG port setup time for TDI

1

—

ns

3

—

ns

JTAG port hold time

10

—

ns

JTAG port clock to output (2)

—15

ns

JTAG port high impedance to valid output (2)

—15

ns

JTAG port valid output to high impedance (2)

—15

ns

Capture register setup time

5

—

ns

Capture register hold time

10

—

ns

Update register clock to output

—

25

ns

Update register high impedance to valid output

—

25

ns

Update register valid output to high impedance

—

25

ns

Notes to Table 1–25:

(1) For more information about JTAG waveforms, refer to “JTAG Waveform” in “Glossary” on page 1–27.

(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V LVTTL/LVCMOS

and 1.5-V LVCMOS, the JTAG port clock to output time is 16 ns.