1–26

Chapter 1: Cyclone III Device Datasheet

I/O Timing

Cyclone III Device Handbook

July 2012

Altera Corporation

Volume 2

I/O Timing

You can use the following methods to determine the I/O timing:

■

the Excel-based I/O Timing.

■

the Quartus II timing analyzer.

The Excel-based I/O Timing provides pin timing performance for each device density

and speed grade. The data is typically used prior to designing the FPGA to get a

timing budget estimation as part of the link timing analysis. The Quartus II timing

analyzer provides a more accurate and precise I/O timing data based on the specifics

of the design after place-and-route is complete.

Delay from output

register to output pin

I/O output

register to

pad

2

0

0.479

0.504

0.915

1.011

1.107

1.018

1.048

ns

Input delay from

dual-purpose clock pin

to fan-out destinations

Pad to global

clock

network

12

0

0.664

0.694

1.199

1.378

1.532

1.392

1.441

ns

Notes to Table 1–37:

(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of the Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software.

(Part 2 of 2)

Parameter

Paths

Affected

Number

of

Settings

Min

Offset

Max Offset

Unit

Fast Corner

Slow Corner

A7, I7

C6

C6

C7

C8

I7

A7

Table 1–38. Cyclone III Devices IOE Programmable Delay on Row Pins

(1), (2)

Parameter

Paths

Affected

Number

of

Settings

Min

Offset

Max Offset

Unit

Fast Corner

Slow Corner

A7, I7

C6

C6

C7

C8

I7

A7

Input delay from pin to

internal cells

Pad to I/O

dataout to

core

7

0

1.209

1.314

2.174

2.335

2.406

2.381

2.505

ns

Input delay from pin to

input register

Pad to I/O

input register

8

0

1.207

1.312

2.202

2.402

2.558

2.447

2.557

ns

Delay from output

register to output pin

I/O output

register to

pad

2

0

0.51

0.537

0.962

1.072

1.167

1.074

1.101

ns

Input delay from

dual-purpose clock pin

to fan-out destinations

Pad to global

clock network

12

0

0.669

0.698

1.207

1.388

1.542

1.403

1.45

ns

Notes to Table 1–38:

(1) The incremental values for the settings are generally linear. For exact values of each setting, use the latest version of Quartus II software.

(2) The minimum and maximum offset timing numbers are in reference to setting ‘0’ as available in the Quartus II software