 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
3.3-VLVCMOS Datasheet(PDF) 24 Page - Altera Corporation |
|
|
|||||||||||||||||||||||||||||
3.3-VLVCMOS Datasheet(HTML) 24 Page - Altera Corporation |
|
|
24 / 34 page  1–24 Chapter 1: Cyclone III Device Datasheet Switching Characteristics Cyclone III Device Handbook July 2012 Altera Corporation Volume 2 Table 1–34 lists the memory output clock jitter specifications for Cyclone III devices. DDR2 SDRAM SSTL-18 Class I 915 410 915 410 1015 510 SSTL-18 Class II 1025 545 1025 545 1125 645 DDR SDRAM SSTL-2 Class I 880 340 880 340 980 440 SSTL-2 Class II 1010 380 1010 380 1110 480 QDRII SRAM 1.8 V HSTL Class I 910 450 910 450 1010 550 1.8 V HSTL Class II 1010 570 1010 570 1110 670 C8 DDR2 SDRAM SSTL-18 Class I 1040 440 1040 440 1140 540 SSTL-18 Class II 1180 600 1180 600 1280 700 DDR SDRAM SSTL-2 Class I 1010 360 1010 360 1110 460 SSTL-2 Class II 1160 410 1160 410 1260 510 QDRII SRAM 1.8 V HSTL Class I 1040 490 1040 490 1140 590 1.8 V HSTL Class II 1190 630 1190 630 1290 730 I7 DDR2 SDRAM SSTL-18 Class I 961 431 961 431 1061 531 SSTL-18 Class II 1076 572 1076 572 1176 672 DDR SDRAM SSTL-2 Class I 924 357 924 357 1024 457 SSTL-2 Class II 1061 399 1061 399 1161 499 QDRII SRAM 1.8 V HSTL Class I 956 473 956 473 1056 573 1.8 V HSTL Class II 1061 599 1061 599 1161 699 A7 DDR2 SDRAM (2) SSTL-18 Class I 1092 462 1092 462 1192 562 SSTL-18 Class II 1239 630 1239 630 1339 730 DDR SDRAM SSTL-2 Class I 1061 378 1061 378 1161 478 SSTL-2 Class II 1218 431 1218 431 1318 531 QDRII SRAM 1.8 V HSTL Class I 1092 515 1092 515 1192 615 1.8 V HSTL Class II 1250 662 1250 662 1350 762 Notes to Table 1–33: (1) Column I/O banks refer to top and bottom I/Os. Row I/O banks refer to right and left I/Os. Wraparound mode refers to the combination of column and row I/Os. (2) For DDR2 SDRAM write timing performance on Columns I/O for C8 and A7 devices, 97.5 degree phase offset is required. Table 1–33. Cyclone III Devices Transmitter Channel-to-Channel Skew (TCCS) – Write Side (1) (Part 2 of 2) Memory Standard I/O Standard Column I/Os (ps) Row I/Os (ps) Wraparound Mode (ps) Lead Lag Lead Lag Lead Lag Table 1–34. Cyclone III Devices Memory Output Clock Jitter Specifications (1), (2) (Part 1 of 2) Parameter Symbol Min Max Unit Clock period jitter tJIT(per) -125 125 ps Cycle-to-cycle period jitter tJIT(cc) -200 200 ps |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
