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3.3-VLVCMOS Datasheet(PDF) 21 Page - Altera Corporation

Part # 3.3-VLVCMOS
Description  This chapterdescribes the electric characteristics, switching characteristics,and I/O timing for Cyclone III devices. A glossary is also included for your reference
PDF  34 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

3.3-VLVCMOS Datasheet(HTML) 21 Page - Altera Corporation

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Chapter 1: Cyclone III Device Datasheet
1–21
Switching Characteristics
July 2012
Altera Corporation
Cyclone III Device Handbook
Volume 2
Table 1–29. Cyclone III Devices True LVDS Transmitter Timing Specifications (1)
Symbol
Modes
C6
C7, I7
C8, A7
Unit
Min
Max
Min
Max
Min
Max
fHSCLK (input
clock frequency)
×10
5
420
5
370
5
320
MHz
×8
5
420
5
370
5
320
MHz
×7
5
420
5
370
5
320
MHz
×4
5
420
5
370
5
320
MHz
×2
5
420
5
370
5
320
MHz
×1
5
420
5
402.5
5
402.5
MHz
HSIODR
×10
100
840
100
740
100
640
Mbps
×8
80
840
80
740
80
640
Mbps
×7
70
840
70
740
70
640
Mbps
×4
40
840
40
740
40
640
Mbps
×2
20
840
20
740
20
640
Mbps
×1
10
420
10
402.5
10
402.5
Mbps
tDUTY
4555
455545
55
%
TCCS
200
200
200
ps
Output jitter
(peak to peak)
500
500
550
ps
tLOCK (2)
—1—1—1
ms
Notes to Table 1–29:
(1) True LVDS transmitter is only supported at the output pin of Row I/O (Banks 1, 2, 5, and 6).
(2) tLOCK is the time required for the PLL to lock from the end of device configuration.
Table 1–30. Cyclone III Devices Emulated LVDS Transmitter Timing Specifications (1) (Part 1 of 2)
Symbol
Modes
C6
C7, I7
C8, A7
Unit
Min
Max
Min
Max
Min
Max
fHSCLK (input
clock frequency)
×10
5
320
5
320
5
275
MHz
×8
5
320
5
320
5
275
MHz
×7
5
320
5
320
5
275
MHz
×4
5
320
5
320
5
275
MHz
×2
5
320
5
320
5
275
MHz
×1
5
402.5
5
402.5
5
402.5
MHz
HSIODR
×10
100
640
100
640
100
550
Mbps
×8
80
640
80
640
80
550
Mbps
×7
70
640
70
640
70
550
Mbps
×4
40
640
40
640
40
550
Mbps
×2
20
640
20
640
20
550
Mbps
×1
10
402.5
10
402.5
10
402.5
Mbps
tDUTY
4555
4555
4555
%
TCCS
200
200
200
ps



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