COMBOSMARTMETER datasheet(24/60 Pages) TI1

24 / 60 page

ADS131E04

ADS131E06

ADS131E08

SBAS561A – JUNE 2012 – REVISED APRIL 2013

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CLOCK

The ADS131E0x provide two different device clocking methods: internal and external. Internal clocking is ideally

suited for low-power, battery-powered systems. The internal oscillator is trimmed for accuracy at room

temperature. Accuracy varies over the specified temperature range; refer to the Electrical Characteristics for

details. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.

The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG1 register enables

and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 4.

The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that

during power-down the external clock be shut down to save power.

Table 4. CLKSEL Pin and CLK_EN Bit

CONFIG1.CLK_EN

CLKSEL PIN

BIT

CLOCK SOURCE

CLK PIN STATUS

External clock

Input: external clock

Internal clock oscillator

3-state

Internal clock oscillator

Output: internal clock oscillator

DATA FORMAT

The ADS131E0x output resolution is dependent upon the DR[2:0] bit setting in the CONFIG1 register. When

DR[2:0] = 000 or 001, the 16 bits of data per channel are sent in binary twos complement format, MSB first. The

LSB has a weight of VREF / (2

15 – 1). A positive full-scale input produces an output code of 7FFFh and the

negative full-scale input produces an output code of 8000h. The output clips at these codes for signals exceeding

full-scale. Table 5 summarizes the ideal output codes for different input signals. All 16 bits toggle when the

analog input is at positive or negative full-scale.

Table 5. Ideal Output Code versus Input Signal, LSB Weight = VREF / (2

15 – 1)

INPUT SIGNAL, VIN

(AINP – AINN)

IDEAL OUTPUT CODE(1)(2)

≥ VREF

7FFFh

+VREF / (2

15 – 1)

0001h

0000h

–VREF / (2

15 – 1)

FFFFh

≤ –VREF (2

15 / 215 – 1)

8000h

(1)

Assumes gain = 1.

(2)

Excludes effects of noise, linearity, offset, and gain error.

When DR[2:0] = 010, 011, 100, 101, or 110, the ADS131E0x outputs 24 bits of data per channel in binary twos

complement format, MSB first. The LSB has a weight of VREF / (2

23 – 1). A positive full-scale input produces an

output code of 7FFFFFh and the negative full-scale input produces an output code of 800000h. The output clips

at these codes for signals exceeding full-scale. Table 6 summarizes the ideal output codes for different input

signals.

Table 6. Ideal Output Code versus Input Signal, LSB Weight = VREF / (2

23 – 1)

INPUT SIGNAL, VIN

(AINP – AINN)

IDEAL OUTPUT CODE

≥ VREF

7FFFFFh

+VREF / (2

23 – 1)

000001h

000000h

–VREF / (2

23 – 1)

FFFFFFh

≤ –VREF (2

23 / 223 – 1)

800000h

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