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COMBOSMARTMETER Datasheet(PDF) 34 Page - Texas Instruments |
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COMBOSMARTMETER Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 60 page ![]() START DRDY CS SCLK DIN DOUT Hi-Z RDATAC Opcode Status Register + n-Channel Data Next Data t UPDATE (1) ADS131E04 ADS131E06 ADS131E08 SBAS561A – JUNE 2012 – REVISED APRIL 2013 www.ti.com START: Start Conversions This opcode starts data conversions. Tie the START pin low to control conversions by command. If conversions are in progress, this command has no effect. The STOP opcode command is used to stop conversions. If the START command is immediately followed by a STOP command, then have a gap of 4 tCLK cycles between them. When the START opcode is sent to the device, keep the START pin low until the STOP command is issued. (See the START subsection of the SPI Interface section for more details.) There are no SCLK rate restrictions for this command and it can be issued at any time. STOP: Stop Conversions This opcode stops conversions. Tie the START pin low to control conversions by command. When the STOP command is sent, the conversion in progress completes and further conversions are stopped. If conversions are already stopped, this command has no effect. There are no SCLK rate restrictions for this command and it can be issued at any time. OFFSETCAL: Channel Offset Calibration This command is used to cancel the channel offset. OFFSETCAL must be executed every time there is a change in PGA gain settings. RDATAC: Read Data Continuous This opcode enables the conversion data output on each DRDY without the need to issue subsequent read data opcodes. This mode places the conversion data in the output register and may be shifted out directly. The read data continuous mode is the default mode of the device and the device defaults in this mode on power-up. RDATAC mode is cancelled by the Stop Read Data Continuous command. If the device is in RDATAC mode, an SDATAC command must be issued before any other commands can be sent to the device. There are no SCLK rate restrictions for this command. However, subsequent data retrieval SCLKs or the SDATAC opcode command should wait at least 4 tCLK cycles for the command to execute. RDATAC timing is shown in Figure 39. As Figure 39 shows, there is a keep out zone of 4 tCLK cycles around the DRDY pulse where this command cannot be issued in. If no data are retrieved from the device, DOUT and DRDY behave similarly in this mode. To retrieve data from the device after the RDATAC command is issued, make sure either the START pin is high or the START command is issued. Figure 39 shows the recommended way to use the RDATAC command. RDATAC is ideally-suited for applications such as data loggers or recorders where registers are set once and do not need to be reconfigured. (1) tUPDATE = 4 / fCLK. Do not read data during this time. Figure 39. RDATAC Usage 34 Submit Documentation Feedback Copyright © 2012–2013, Texas Instruments Incorporated Product Folder Links: ADS131E04 ADS131E06 ADS131E08 |
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