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AM79C972BVCW Datasheet(PDF) 30 Page - Advanced Micro Devices |
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AM79C972BVCW Datasheet(HTML) 30 Page - Advanced Micro Devices |
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30 / 130 page ![]() 30 Am79C972 Expansion ROM Transfers The host must initialize the Expansion ROM Base Ad- dress register at offset 30H in the PCI configuration space with a valid address before enabling the access to the device. The Am79C972 controller will not react to any access to the Expansion ROM until both MEMEN (PCI Command register, bit 1) and ROMEN (PCI Ex- pansion ROM Base Address register, bit 0) are set to 1. After the Expansion ROM is enabled, the Am79C972 controller will assert DEVSEL on all memory read ac- cesses with an address between ROMBASE and ROMBASE + 1M - 4. The Am79C972 controller aliases all accesses to the Expansion ROM of the command types Memory Read Multiple and Memory Read Line to the basic Memory Read command. Eight-bit, 16-bit, and 32-bit read transfers are supported. Since setting MEMEN also enables memory mapped access to the I/O resources, attention must be given the PCI Memory Mapped I/O Base Address register before enabling access to the Expansion ROM. The host must set the PCI Memory Mapped I/O Base Ad- dress register to a value that prevents the Am79C972 controller from claiming any memory cycles not in- tended for it. The Am79C972 controller will always read four bytes for every host Expansion ROM read access. TRDY will not be asserted until all four bytes are loaded into an in- ternal scratch register. The cycle TRDY is asserted de- pends on the programming of the Expansion ROM interface timing. The following figure (Figure 5) as- sumes that ROMTMG (BCR18, bits 15-12) is at its de- fault value. Note: The Expansion ROM should be read only during PCI configuration time for the PCI system. When the host tries to write to the Expansion ROM, the Am79C972 controller will claim the cycle by asserting DEVSEL. TRDY will be asserted one clock cycle later. The write operation will have no effect. Writes to the Ex- pansion ROM are done through the BCR30 Expansion Bus Data Port. See the section on the Expansion Bus Interface for more details. See Figure 5. Figure 5. Expansion ROM Read FRAME CLK AD IRDY TRDY C/BE DEVSEL STOP PAR ADDR CMD PAR 1 2345 48 49 50 51 DATA PAR BE DEVSEL is sampled 21485C-8 |
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