AM79C972BVCW datasheet(67/130 Pages) AMD

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Am79C972

Media Independent Interface

The Am79C972 controller fully supports the MII ac-

cording to the IEEE 802.3 standard. This Reconcilia-

tion Sublayer interface allows a variety of PHYs

(10 0 BASE-T X , 100 BASE-F X , 100BASE-T 4 ,

100BASE-T2, 10BASE-T, etc.) to be attached to the

Am79C972 MAC engine without future upgrade prob-

lems. The MII interface is a 4-bit (nibble) wide data path

interface that runs at 25 MHz for 100-Mbps networks or

2.5 MHz for 10-Mbps networks. The interface consists

of two independent data paths, receive (RXD(3:0)) and

transmit (TXD(3:0)), control signals for each data path

(RX_ER, RX_DV, TX_ER, TX_EN), network status sig-

nals (COL, CRS), clocks (RX_CLK, TX_CLK) for each

data path, and a two-wire management interface (MDC

and MDIO). See Figure 35.

MII Transmit Interface

The MII transmit clock is generated by the external

PHY and is sent to the Am79C972 controller on the

TX_CLK input pin. The clock can run at 25 MHz or 2.5

MHz, depending on the speed of the network to which

the external PHY is attached. The data is a nibble-wide

(4 bits) data path, TXD(3:0), from the Am79C972 con-

troller to the external PHY and is synchronous to the

rising edge of TX_CLK. The transmit process starts

when the Am79C972 controller asserts the TX_EN,

which indicates to the external PHY that the data on

TXD(3:0) is valid.

Normally, unrecoverable errors are signaled through

the MII to the external PHY with the TX_ER output pin.

The external PHY will respond to this error by generat-

ing a TX coding error on the current transmitted frame.

The Am79C972 controller does not use this method of

signaling errors on the transmit side. The Am79C972

controller will invert the FCS on the last byte generating

an invalid FCS. The TX_ER pin is reserved for future

use and is actively driven to 0.

MII Receive Interface

The MII receive clock is also generated by the external

PHY and is sent to the Am79C972 controller on the

RX_CLK input pin. The clock will be the same fre-

quency as the TX_CLK but will be out of phase and can

run at 25 MHz or 2.5 MHz, depending on the speed of

the network to which the external PHY is attached.

Figure 35.

Media Independent Interface

The RX_CLK is a continuous clock during the reception

of the frame, but can be stopped for up to two RX_CLK

periods at the beginning and the end of frames, so that

the external PHY can sync up to the network data traffic

necessary to recover the receive clock. During this

time, the external PHY may switch to the TX_CLK to

maintain a stable clock on the receive interface. The

Am79C972 controller will handle this situation with no

loss of data. The data is a nibble-wide (4 bits) data

pa th, RXD (3:0 ), from the exter n al PHY to th e

Am79C972 controller and is synchronous to the rising

edge of RX_CLK.

The receive process starts when RX_DV is asserted.

RX_DV will remain asserted until the end of the receive

frame. The Am79C972 controller requires CRS (Car-

rier Sense) to toggle in between frames in order to re-

ceive them properly. Errors in the currently received

frame are signaled across the MII by the RX_ER pin.

RX_ER can be used to signal special conditions out of

band when RX_DV is not asserted. Two defined out-of-

band conditions for this are the 100BASE-TX signaling

of bad Start of Frame Delimiter and the 100BASE-T4

indication of illegal code group before the receiver has

synched to the incoming data. The Am79C972 control-

ler will not respond to these conditions. All out of band

RXD(3:0)

RX_DV

RX_ER

RX_CLK

TXD(3:0)

TX_EN

Am79C972

COL

CRS

Receive Signals

Transmit Signals

Management Port Signals

Network Status Signals

TX_CLK

MDIO

MDC

21485C-38

AM79C972BVCW Datasheet(PDF) 67 Page - Advanced Micro Devices

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