AM79C972BVCW datasheet(74/130 Pages) AMD

74 / 130 page

Am79C972

AS_EBOE

driven

high

for

one-half

clock,

EBUA_EBA[7:0] are driven with the upper 8 bits of the

Expansion ROM address for one more clock cycle after

AS_EBOE goes low. Next, the Am79C972 controller

starts driving the lower 8 bits of the Expansion ROM

address on EBUA_EBA[7:0].

The time that the Am79C972 controller waits for data to

be valid is programmable. ROMTMG (BCR18, bits 15-

12) defines the time from when the Am79C972 control-

ler drives EBUA_EBA[7:0] with the lower 8 bits of the

Expansion ROM address to when the Am79C972 con-

troller latches in the data on the EBD[7:0] inputs. The

cles. When ROMTMG is set to nine (the default value),

EBD[7:0] is sampled with the next rising edge of CLK

ten clock cycles after EBUA_EBA[7:0] was driven with

a new address value. The clock edge that is used to

sample the data is also the clock edge that generates

the next Expansion ROM address. All four bytes of Ex-

pansion ROM data are stored in holding registers. One

clock cycle after the last data byte is available, the

Am79C972 controller asserts TRDY.

Figure 39.

Flash Configuration for the Expansion Bus

The access time for the Expansion ROM or the EB-

DATA (BCR30) device (tACC) during read operations

can be calculated by subtracting the clock to output

delay for the EBUA_EBA[7:0] outputs (tv_A_D) and by

subtracting the input to clock setup time for the

EBD[7:0] inputs (ts_D) from the time defined by

ROMTMG:

tACC = ROMTMG * CLK period *CLK_FAC - (tv_A_D) -

(ts_D)

The access time for the Expansion ROM or for the EB-

DATA (BCR30) device (tACC) during write operations

can be calculated by subtracting the clock to output

delay for the EBUA EBA[7:0] outputs (tv_A_D) and by

EBUA_EBA[7:0]

EBDA[15:8]

EBD[7:0]

EBWE

AS_/EBOE

A[15:8]

A[7:0]

DQ[7:0]

Am79C972

’374

D-FF

FLASH

EROMCS

A[23:16]

21485C-42

AM79C972BVCW Datasheet(PDF) 74 Page - Advanced Micro Devices

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