AM79C972BVCW datasheet(43/130 Pages) AMD

43 / 130 page

Am79C972

Whenever the Am79C972 controller is the current bus

master and a data parity error occurs, SINT (CSR5, bit

11) will be set to 1. When SINT is set, INTA is asserted

if the enable bit SINTE (CSR5, bit 10) is set to 1. This

mechanism can be used to inform the driver of the sys-

tem error. The host can read the PCI Status register to

determine the exact cause of the interrupt. The setting

of SINT due to a data parity error is not dependent on

the setting of PERREN (PCI Command register, bit 6).

By default, a data parity error does not affect the state

of the MAC engine. The Am79C972 controller treats the

data in all bus master transfers that have a parity error

as if nothing has happened. All network activity contin-

ues.

Advanced Parity Error Handling

For all DMA cycles, the Am79C972 controller provides

a second, more advanced level of parity error handling.

This mode is enabled by setting APERREN (BCR20, bit

10) to 1. When APERREN is set to 1, the BPE bits

(RMD1 and TMD1, bit 23) are used to indicate parity

error in data transfers to the receive and transmit buff-

ers. Note that since the advanced parity error handling

uses an additional bit in the descriptor, SWSTYLE

(BCR20, bits 7-0) must be set to 2 or 3 to program the

Am79C972 controller to use 32-bit software structures.

The Am79C972 controller will react in the following way

when a data parity error occurs:

n Initialization block read: STOP (CSR0, bit 2) is set to

1 and causes a STOP_RESET of the device.

n Descriptor ring read: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to 1 to cause a STOP_RESET

of the device.

n Descriptor ring write: Any on-going network activity

is terminated in an orderly sequence and then STOP

(CSR0, bit 2) is set to 1 to cause a STOP_RESET

of the device.

n Transmit buffer read: BPE (TMD1, bit 23) is set in

the current transmit descriptor. Any on-going net-

work transmission is terminated in an orderly se-

quence.

n Receive buffer write: BPE (RMD1, bit 23) is set in

the last receive descriptor associated with the frame.

Terminating on-going network transmission in an or-

derly sequence means that if less than 512 bits have

been transmitted onto the network, the transmission

will be terminated immediately, generating a runt

packet.

If 512 bits or more have been transmitted, the message

will have the current FCS inverted and appended at the

next byte boundary to guarantee an FCS error is de-

tected at the receiving station.

APERREN does not affect the reporting of address

parity errors or data parity errors that occur when the

Am79C972 controller is the target of the transfer.

Initialization Block DMA Transfers

During execution of the Am79C972 controller bus mas-

ter initialization procedure, the Am79C972 microcode

will repeatedly request DMA transfers from the BIU.

During each of these initialization block DMA transfers,

the BIU will perform two data transfer cycles reading

one DWord per transfer and then it will relinquish the

bus. When SSIZE32 (BCR20, bit 8) is set to 1 (i.e., the

initialization block is organized as 32-bit software struc-

tures), there are seven DWords to transfer during the

bus master initialization procedure, so four bus master-

ship periods are needed in order to complete the initial-

ization sequence. Note that the last DWord transfer of

the last bus mastership period of the initialization se-

quence accesses an unneeded location. Data from this

transfer is discarded internally. When SSIZE32 is

cleared to 0 (i.e., the initialization block is organized as

16-bit software structures), then three bus mastership

periods are needed to complete the initialization se-

quence.

The Am79C972 supports two transfer modes for read-

ing the initialization block: non-burst and burst mode,

with burst mode being the preferred mode when the

Am79C972 controller is used in a PCI bus application.

See Figure 23 and Figure 24.

When BREADE is cleared to 0 (BCR18, bit 6), all initial-

ization block read transfers will be executed in non-

burst mode. There is a new address phase for every

data phase. FRAME will be dropped between the two

transfers. The two phases within a bus mastership pe-

riod will have addresses of ascending contiguous or-

der.

When BREADE is set to 1 (BCR18, bit 6), all initializa-

tion block read transfers will be executed in burst mode.

AD[1:0] will be 0 during the address phase indicating a

linear burst order.

AM79C972BVCW Datasheet(PDF) 43 Page - Advanced Micro Devices

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