AM188ES-40VCSLASHW datasheet(48/102 Pages) AMD

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Am186/188ES and Am186/188ESLV Microcontrollers

PRELIMINA R Y

INTERRUPT CONTROL UNIT

The Am186ES and Am188ES microcontrollers can re-

ceive interrupt requests from a variety of sources, both

internal and external. The internal interrupt controller

arranges these requests by priority and presents them

one at a time to the CPU.

There are up to eight external interrupt sources on the

Am186ES and Am188ES microcontrollers—seven

maskable interrupt pins and one nonmaskable interrupt

(NMI) pin. In addition, there are eight internal interrupt

sources (three timers, two DMA channels, the two

asynchronous serial ports, and the Watchdog Timer

NMI) that are not connected to external pins. INT5 and

INT6 are multiplexed with DRQ0 and DRQ1. These two

interrupts are available if the associated DMA is not en-

abled or is being used with internal synchronization.

The Am186ES and Am188ES microcontrollers provide

up to six interrupt sources not present on the 80C186

and 80C188 microcontrollers. There are up to three ad-

ditional external interrupt pins—INT4, INT5, and INT6.

These pins operate much like the INT3–INT0 interrupt

pins on the 80C186 and 80C188 microcontrollers.

There are also two internal interrupts from the serial

ports and the watchdog timer can generate interrupts.

The seven maskable interrupt request pins can be

used as direct interrupt requests. INT4–INT0 can be ei-

ther edge triggered or level triggered. INT6 and INT5

are edge triggered only. In addition, INT0 and INT1 can

be configured in cascade mode for use with an external

82C59A-compatible interrupt controller. When INT0 is

configured in cascade mode, the INT2 pin is automati-

cally configured in its INTA0 function. When INT1 is

configured in cascade mode, the INT3 pin is automati-

cally configured in its INTA1 function. An external inter-

rupt controller can be used as the system master by

programming the internal interrupt controller to operate

in slave mode. INT6–INT4 are not available in slave

mode.

Interrupts are automatically disabled when an interrupt

is taken. Interrupt-service routines (ISRs) may

re-enable interrupts by setting the IF flag. This allows

interrupts of greater or equal priority to interrupt the

currently executing ISR. Interrupts from the same

source are disabled as long as the corresponding bit in

the interrupt in-service register is set. INT1 and INT0

provide a special bit to enable special fully nested

mode. When configured in special fully nested mode,

the interrupt source may generate a new interrupt

regardless of the setting of the in-service bit.

TIMER CONTROL UNIT

There are three 16-bit programmable timers and a

watchdog timer on the Am186ES and Am188ES micro-

controllers.

Timer 0 and timer 1 are connected to four external pins

(each one has an input and an output). These two tim-

ers can be used to count or time external events, or to

generate nonrepetitive or variable-duty-cycle wave-

forms. When pulse width demodulation is enabled,

timer 0 and timer 1 are used to measure the width of

the High and Low pulses on the PWD pin. (See the

Pulse Width Demodulation section on page 51.)

Timer 2 is not connected to any external pins. It can be

used for real-time coding and time-delay applications.

It can also be used as a prescaler to timers 0 and 1 or

to synchronize DMA transfers.

The programmable timers are controlled by eleven 16-

bit registers in the peripheral control block. A timer’s

timer-count register contains the current value of that

timer. The timer-count register can be read or written

with a value at any time, whether the timer is running or

not. The microcontroller increments the value of the

timer-count register each time a timer event occurs.

Each timer also has a maximum-count register that de-

fines the maximum value the timer can reach. When

the timer reaches the maximum value, it resets to 0

during the same clock cycle. The value in the maxi-

mum-count register is never stored in the timer-count

mum-count register. Using both the primary and sec-

ondary maximum-count registers lets the timer

alternate between two maximum values.

If the timer is programmed to use only the primary max-

imum-count register, the timer output pin switches Low

for one clock cycle after the maximum value is

reached. If the timer is programmed to use both of its

maximum-count registers, the output pin indicates

which maximum-count register is currently in control,

thereby creating a waveform. The duty cycle of the

waveform depends on the values in the maximum-

count registers.

Each timer is serviced every fourth clock cycle, so a

timer can operate at a speed of up to one-quarter of the

internal clock frequency. A timer can be clocked exter-

nally at this same frequency; however, because of in-

ternal synchronization and pipelining of the timer

circuitry, the timer output can take up to six clock cycles

to respond to the clock or gate input.

AM188ES-40VC/W Datasheet(PDF) 48 Page - Advanced Micro Devices

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