PIC18F4550ESOSQTP datasheet(169/430 Pages) MICROCHIP

169 / 430 page

Preliminary

DS39632D-page 167

PIC18F2455/2550/4455/4550

TABLE 17-1:

DIFFERENTIAL OUTPUTS TO

TRANSCEIVER

TABLE 17-2:

SINGLE-ENDED INPUTS

FROM TRANSCEIVER

The UOE signal toggles the state of the external trans-

ceiver. This line is pulled low by the device to enable

the transmission of data from the SIE to an external

device.

17.2.2.3

Internal Pull-up Resistors

The PIC18FX455/X550 devices have built-in pull-up

resistors designed to meet the requirements for

low-speed and full-speed USB. The UPUEN bit

(UCFG<4>) enables the internal pull-ups. Figure 17-1

shows the pull-ups and their control.

17.2.2.4

External Pull-up Resistors

External pull-up may also be used. The VUSB pin may be

used to pull up D+ or D-. The pull-up resistor must be

1.5 k

Ω (±5%) as required by the USB specifications.

Figure 17-3 shows an example.

FIGURE 17-3:

EXTERNAL CIRCUITRY

17.2.2.5

Ping-Pong Buffer Configuration

The usage of ping-pong buffers is configured using the

PPB1:PPB0 bits. Refer to Section 17.4.4 “Ping-Pong

Buffering” for a complete explanation of the ping-pong

buffers.

17.2.2.6

USB Output Enable Monitor

The USB OE monitor provides indication as to whether

the SIE is listening to the bus or actively driving the bus.

This is enabled by default when using an external

transceiver or when UCFG<6> = 1.

The USB OE monitoring is useful for initial system

debugging, as well as scope triggering during eye

pattern generation tests.

17.2.2.7

Eye Pattern Test Enable

An automatic eye pattern test can be generated by the

module when the UCFG<7> bit is set. The eye pattern

output will be observable based on module settings,

meaning that the user is first responsible for configuring

the SIE clock settings, pull-up resistor and Transceiver

mode. In addition, the module has to be enabled.

Once UTEYE is set, the module emulates a switch from

a receive to transmit state and will start transmitting a

J-K-J-K bit sequence (K-J-K-J for full speed). The

sequence will be repeated indefinitely while the Eye

Pattern Test mode is enabled.

Note that this bit should never be set while the module

is connected to an actual USB system. This test mode

is intended for board verification to aid with USB certi-

fication tests. It is intended to show a system developer

the noise integrity of the USB signals which can be

affected by board traces, impedance mismatches and

proximity to other system components. It does not

properly test the transition from a receive to a transmit

state. Although the eye pattern is not meant to replace

the more complex USB certification test, it should aid

during first order system debugging.

17.2.2.8

Internal Regulator

The PIC18FX455/X550 devices have a built-in 3.3V reg-

ulator to provide power to the internal transceiver and

provide a source for the internal/external pull-ups. An

external 220 nF (±20%) capacitor is required for stability.

The regulator is enabled by default and can be disabled

through the VREGEN Configuration bit. When enabled,

the voltage is visible on pin VUSB. When the regulator

is disabled, a 3.3V source must be provided through

the VUSB pin for the internal transceiver. If the internal

transceiver is disabled, VUSB is not used.

VPO

VMO

Bus State

Single-Ended Zero

Differential ‘0’

Differential ‘1’

Illegal Condition

Bus State

Single-Ended Zero

Low Speed

High Speed

Error

PIC®

Microcontroller

Host

Controller/HUB

VUSB

D+

D-

Note:

The above setting shows a typical connection

for a full-speed configuration using an on-chip

regulator and an external pull-up resistor.

1.5 k

Note:

The drive from VUSB is sufficient to only

drive an external pull-up in addition to the

internal transceiver.

Note 1: Do not enable the internal regulator if an

external regulator is connected to VUSB.

2: VDD must be greater than VUSB at all

times, even with the regulator disabled.

PIC18F4550ESOSQTP Datasheet(PDF) 169 Page - Microchip Technology

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