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PIC18F4550ESOSQTP Datasheet(PDF) 170 Page - Microchip Technology

Part # PIC18F4550ESOSQTP
Description  28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology
PDF  430 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F4550ESOSQTP Datasheet(HTML) 170 Page - Microchip Technology

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PIC18F2455/2550/4455/4550
DS39632D-page 168
Preliminary
© 2007 Microchip Technology Inc.
17.2.3
USB STATUS REGISTER (USTAT)
The USB Status register reports the transaction status
within the SIE. When the SIE issues a USB transfer
complete interrupt, USTAT should be read to determine
the status of the transfer. USTAT contains the transfer
endpoint number, direction and Ping-Pong Buffer
Pointer value (if used).
The USTAT register is actually a read window into a
four-byte status FIFO, maintained by the SIE. It allows
the microcontroller to process one transfer while the
SIE processes additional endpoints (Figure 17-4).
When the SIE completes using a buffer for reading or
writing data, it updates the USTAT register. If another
USB transfer is performed before a transaction
complete interrupt is serviced, the SIE will store the
status of the next transfer into the status FIFO.
Clearing the transfer complete flag bit, TRNIF, causes
the SIE to advance the FIFO. If the next data in the
FIFO holding register is valid, the SIE will immediately
reassert the interrupt. If no additional data is present,
TRNIF will remain clear; USTAT data will no longer be
reliable.
FIGURE 17-4:
USTAT FIFO
Note:
The data in the USB Status register is valid
only when the TRNIF interrupt flag is
asserted.
Note:
If an endpoint request is received while the
USTAT
FIFO
is
full,
the
SIE
will
automatically issue a NAK back to the
host.
Data Bus
USTAT from SIE
4-byte FIFO
for USTAT
Clearing TRNIF
Advances FIFO
REGISTER 17-3:
USTAT: USB STATUS REGISTER
U-0
R-x
R-x
R-x
R-x
R-x
R-x
U-0
—
ENDP3
ENDP2
ENDP1
ENDP0
DIR
PPBI(1)
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-3
ENDP3:ENDP0: Encoded Number of Last Endpoint Activity bits
(represents the number of the BDT updated by the last USB transfer)
1111
= Endpoint 15
1110
= Endpoint 14
....
0001
= Endpoint 1
0000
= Endpoint 0
bit 2
DIR: Last BD Direction Indicator bit
1
= The last transaction was an IN token
0
= The last transaction was an OUT or SETUP token
bit 1
PPBI: Ping-Pong BD Pointer Indicator bit(1)
1
= The last transaction was to the Odd BD bank
0
= The last transaction was to the Even BD bank
bit 0
Unimplemented: Read as ‘0’
Note 1:
This bit is only valid for endpoints with available Even and Odd BD registers.



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