12

TS68C429A

2120A–HIREL–08/02

Figure 5. Write Cycle

3. LDS/UDS can be asserted on the same or previous CLK-SYS period as CS but (3) and (4) must be met.

Figure 6. Interrupt Cycle (IEIxx = 0)

Notes:

1. If UDS = 1, D15-D8 stay hi-z else D15-D8 drive the bus with a stable unknown value.

2. If IEOxx goes low, neither vector nor DTACK are generated, else IEOxx stays inactive and a vector is generated (D7-D0 and

DTACK).