TS68C429AMFBSLASHC datasheet(31/43 Pages) ATMEL

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TS68C429A

2120A–HIREL–08/02

1: Self-test fail.

bit 13: Result of Transmitter 3 self-test:

0: (if bit 10 is set to 1) self-test pass,

1: Self-test fail.

bit 14: 0: Receiver Label Control Matrix self-test is running,

1: End of receiver Label Control Matrix self-test.

bit 15: Result of receiver LCM self-test:

0: (if bit 14 is set to 1) self-test pass,

1: Self-test fail.

Self-test Use

The self-test destroys the content of the tested memory. So, it could be used after sys-

tem reset, during system initialization. Only one self-test (transmitters and receivers)

can be performed after a reset. If the self-test must be restarted, the reset must be acti-

vated (then released) before the new self-test start.

To program the self-test:

If the receiver self-test will be used:

set to 1 LCMWE bits (for all receivers).

If receiver self-test will be used and CLK-SYS is > 10 MHz:

set to self-test register bit 5.

Start self-test:

set to 1 self-test register bit 6 for Transmitter test,

set to 1 self-test register bit 7 for Receiver RAM test.

At this point, self-test is running. The test duration is:

710 CLK-SYS periods for Transmitter self-test,

2820 CLK-SYS periods for Receiver RAM test if self-test register bit 5 is 0,

5640 CLK-SYS periods for Receiver RAM test if self-test register bit 5 is 1.

To read the self-test result, the user must:

poll the self-test register and wait for an end of test set to 1 (bits 8 to 10, bit 14)

then,

read the self-test register again to have a valid result on bits 11, 12, 13, 15

according to the tests which end at point 1.

Memory MAP

Address

Access

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Receiving channel 1

R/W

Receiver-control-register

Gap-register

Message-buffer MSW

Message-buffer LSW

Receiving channel 2

TS68C429AMFB/C Datasheet(PDF) 31 Page - ATMEL Corporation

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