TS68C429AMFBSLASHC datasheet(24/43 Pages) ATMEL

24 / 43 page

TS68C429A

2120A–HIREL–08/02

• FIFO

The FIFO is seen as two 16-bit words. The Most Significant Word (MSW) must be writ-

ten first. The Least Significant Word (LSW) write increments the FIFO counter.

Before any write, the user should verify that the FIFO is not full. If the FIFO is full, any

write to the FIFO will be lost.

General Circuit Control

Logical Control Unit (LCU)

The LCU mainly distributes the clocks and reset within the MRT. The reset signal, active

low is an asynchronous signal. When it occurs, all registers are reset to zero except the

Label-Control-Matrix which is not initialized and the Status-Register which is set to FC00

(hex). Reset duration must be greater than 4 clk-cyc periods.

The LCU contains the Status-register. This read/write register indicates the state of the

internal operations. It is also the image of the pending interrupts if they are not masked.

Clearing a bit “RX-Channel-i” will cancel the received message and release the Mes-

sage-buffer for reception of a new message. The “End of TX on channel-i” Is set only

when the involved channel FIFO is empty. The format of the Status-Register is given

below.

Figure 19. Status Register

TS68C429AMFB/C Datasheet(PDF) 24 Page - ATMEL Corporation