Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

CS44L10 Datasheet(PDF) 13 Page - Cirrus Logic

Part # CS44L10
Description  Digital PWH Headphone Monitor
PDF  34 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS44L10 Datasheet(HTML) 13 Page - Cirrus Logic

Back Button CS44L10 Datasheet HTML 9Page - Cirrus Logic CS44L10 Datasheet HTML 10Page - Cirrus Logic CS44L10 Datasheet HTML 11Page - Cirrus Logic CS44L10 Datasheet HTML 12Page - Cirrus Logic CS44L10 Datasheet HTML 13Page - Cirrus Logic CS44L10 Datasheet HTML 14Page - Cirrus Logic CS44L10 Datasheet HTML 15Page - Cirrus Logic CS44L10 Datasheet HTML 16Page - Cirrus Logic CS44L10 Datasheet HTML 17Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 13 / 34 page
background image
CS44L10
DS541PP1
13
4. REGISTER DESCRIPTIONS
4.1 Power and Muting Control (address 02h)
4.1.1 SOFT RAMP AND ZERO CROSS CONTROL (SZC)
Default = 10
00 - Immediate Change
01 - Zero Cross Control
10 - Ramped Control
11 - Reserved
Function:
Immediate Change
When Immediate Change is selected, all level changes will take effect immediately in one step.
Zero Cross Control
Zero Cross Enable dictates that signal level changes, either by attenuation changes or muting, will occur
on a signal zero crossing to minimize audible artifacts. The requested level change will occur after a
time-out period of 512 sample periods (10.7 ms at 48 kHz sample rate) if the signal does not encounter a
zero crossing. The zero cross function is independently monitored and implemented for each channel.
Ramped Control
Soft Ramp allows level changes, both muting and attenuation, to be implemented by incrementally ramp-
ing, in 1/8 dB steps, from the current level to the new level at a rate of 1 dB per 8 left/right clock periods.
Note: Ramped Control is not available in Double Speed Mode.
4.1.2 POWER DOWN (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port mode can occur.
76543
210
SZC1
SZC0
PDN
FLT
RUPBYP
RDNBYP
Reserved
Reserved
10100
000



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com