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CS44L10 Datasheet(PDF) 22 Page - Cirrus Logic |
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CS44L10 Datasheet(HTML) 22 Page - Cirrus Logic |
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22 / 34 page ![]() CS44L10 22 DS541PP1 4.9.5 DE-EMPHASIS CONTROL (DEM) Default = 00 00 - Disabled 01 - 44.1 kHz 10 - 48 kHz 11 - 32 kHz Function: Selects the appropriate digital filter to maintain the standard 15 µs/50 µs digital de-emphasis filter re- sponse at 32, 44.1 or 48 kHz sample rates (see Figure 6). Note: De-emphasis is not available in double speed mode. LRCK (kHz) MCLK/ LRCK MCLK (MHz) PWM Switching Freq. (kHz) 48 256 12.288 48 384 18.432 384 48 512 24.576 44.1 256 11.2896 44.1 384 16.9344 352.8 44.1 512 22.5792 32 1024 32.768 512 24 1024 24.576 12 2048 24.576 8 1536 12.288 384 8 2304 18.432 8 3072 24.576 Table 12. Single Speed Clock Modes - Stand-Alone Mode DBS = 1 MCLKDIV = 0 DBS = 1 MCLKDIV = 1 LRCK (kHz) MCLK/ LRCK MCLK (MHz) MCLK/ LRCK MCLK (MHz) FRQSFT1 FRQSFT0 CLKDIV1 CLKDIV0 PWM Switching Freq. (kHz) 96 128 12.288 256 24.576 0000 96 192 18.432 384 36.864 0001 384 96 256 24.576 512 49.152 0010 Table 13. Double Speed Clock Modes - Control Port Mode LRCK (kHz) MCLK/ LRCK MCLK (MHz) PWM Switching Freq. (kHz) 96 128 12.288 384 96 192 18.432 Table 14. Double Speed Clock Modes - Stand-Alone Mode |
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