CS44L10

DS541PP1

25

5. PIN DESCRIPTION

1

2

3

4

5

6

7

8

9

10

11

12

13

14

16

15

Serial Data

SDIN

RST

Reset

Left/Right Clock

LRCK

GND

Headphone B Ground

Serial Clock

SCLK

HP_B

Headphone B Output

Master Clock

MCLK

VA_HPB

Headphone B Power

Digital Power

VD

VA_HPA

Headphone A Power

Ground

GND

HP_A

Headphone A Output

Interface Power

VL

GND

Headphone A Ground

SCL/DIF0

SCL/DIF0

SDA/DEM

SDA/DEM

SDIN

1

Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK

2

Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the

serial audio data line. The frequency of the left/right clock must be at the audio sample rate, Fs.

SCLK

3

Serial Clock (Input) - Serial clock for the serial audio interface.

MCLK

4

Master Clock (Input) - Clock source for the PWM modulator and digital filters. Table 11, 12, 13

and 14 illustrate several standard audio sample rates and required master clock frequencies.

VD

5

Digital Power (Input) - Positive power supply for the digital section. Refer to "Recommended

Operating Conditions" for appropriate voltages.

GND

6, 10

& 15

Ground (Input) - Ground Reference.

VL

7

Logic Power (Input) - Determines the required signal level for the digital input/output. Refer to

"Recommended Operating Conditions" for appropriate voltages.

HP_A

HP_B

11

14

Headphone Outputs (Output) - PWM Headphone Outputs. An external LC filter should be

added to suppress high frequency switching noise. A DC blocking capacitor is also required.

Refer to Typical Connection Diagrams.

VA_HPA

VA_HPB

12

13

Headphone Amplifier Power (Input) - Positive power supply for the headphone amplifier.

Refer to "Recommended Operating Conditions" for appropriate voltages.

RST

16

Reset (Input) - The device enters a low power mode and all internal registers are reset to their

default settings when low. The control port cannot be accessed when Reset is low. See Sec-

tion 6.5

Control Port

Definitions

SCL

8

Serial Control Port Clock (Input) - Serial clock for the serial control port. Requires an external

pull-up resistor to VL in Two-Wire mode.

SDA

9

Serial Control Data (Input/Output) - SDA is a data I/O line in Two-Wire mode and requires an

external pull-up resistor to the logic interface voltage.

Stand Alone

Definitions

DIF0

8

Digital Interface Format (Input) - The required relationship between the Left/Right clock, serial

clock and serial data is defined by the Digital Interface Format and the options are detailed

below

DEM

9

De-emphasis Control (Input) - Selects the standard 15

µs/50 µs digital de-emphasis filter

response at 44.1 kHz sample rates. NOTE: De-emphasis is not available in Double or Quad

Speed Modes. When DEM is grounded, de-emphasis is disabled.

DIF0

DESCRIPTION

FIGURE

0

18

1

Right Justified, 16-bit Data

19

Table 15. Digital Interface Format (Stand-Alone Mode)