 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
LPC1547JBD48 Datasheet(PDF) 22 Page - NXP Semiconductors |
|
|
|||||||||||||||||||||||||||||
LPC1547JBD48 Datasheet(HTML) 22 Page - NXP Semiconductors |
|
|
22 / 99 page  LPC15XX All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 1 — 19 February 2014 22 of 99 NXP Semiconductors LPC15xx 32-bit ARM Cortex-M3 microcontroller 8.3 On-chip flash programming memory The LPC15xx contain up to 256 kB on-chip flash program memory. The flash can be programmed using In-System Programming (ISP) or In-Application Programming (IAP) via the on-chip boot loader software. Flash updates via USB are supported as well. The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages. Individual pages of 256 byte each can be erased using the IAP erase page command. 8.3.1 ISP pin configuration The LPC15xx supports ISP via the USART0, C_CAN, or USB interfaces. The ISP mode is determined by the state of two pins (ISP_0 and ISP_1) at boot time: The ISP pin assignment is different for each package, so that the fewest functions possible are blocked. No more than four pins must be set aside for entering ISP in any ISP mode. The boot code assigns two ISP pins for each package, which are probed when the part boots to determine whether or not to enter ISP mode. Once the ISP mode has been determined, the boot loader configures the necessary serial pins for each package. Pins which are not configured by the boot loader for the selected boot mode (for example CAN0_RD and CAN0_TD in USART mode) can be assigned to any function through the switch matrix. 8.4 EEPROM The LPC15xx contain 4 kB of on-chip byte-erasable and byte-programmable EEPROM data memory. The EEPROM can be programmed using In-Application Programming (IAP) via the on-chip boot loader software. Table 6. ISP modes Boot mode ISP_0 ISP_1 Description No ISP HIGH HIGH ISP bypassed. Part attempts to boot from flash. If the user code in flash is not valid, then enters ISP via USB. C_CAN HIGH LOW Part enters ISP via C_CAN. USB LOW HIGH Part enters ISP via USB. USART0 LOW LOW Part enters ISP via USART0. Table 7. Pin assignments for ISP modes Boot pin LQFP48 LQFP64 LQFP100 ISP_0 PIO0_4 PIO1_9 PIO2_5 ISP_1 PIO0_16 PIO1_11 PIO2_4 USART mode U0_TXD PIO0_15 PIO0_18 PIO2_6 U0_RXD PIO0_14 PIO0_13 PIO2_7 C_CAN mode CAN0_TD PIO0_18 PIO0_31 PIO2_8 CAN0_RD PIO0_13 PIO0_11 PIO2_9 USB mode USB_VBUS (same as ISP_1) PIO0_16 PIO1_11 PIO2_4 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
