LPC1547JBD48 datasheet(60/99 Pages) NXP

60 / 99 page

LPC15XX

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Product data sheet

Rev. 1 — 19 February 2014

60 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

Conditions: VDD = 3.3 V; active mode entered executing code while(1){} from flash; all

peripherals disabled in the SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal

pull-up resistors disabled; BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz to 72 MHz: IRC enabled; PLL enabled.

Fig 19. Active mode: Typical supply current IDD versus temperature

Conditions: VDD = 3.3 V; sleep mode entered from flash; all peripherals disabled in the

SYSAHBCLKCTRL0/1 registers; all peripheral clocks disabled; internal pull-up resistors disabled;

BOD disabled; low-current mode.

1 MHz - 6 MHz: IRC enabled; PLL disabled.

12 MHz: IRC enabled; PLL disabled.

24 MHz to 72 MHz: IRC enabled; PLL enabled.

Fig 20. Sleep mode: Typical supply current IDD versus temperature for different system

clock frequencies

aaa-011385

-40

-10

110

temperature (°C)

IDD

(mA)

12 MHz

24 MHz

48 MHz

60 MHz

72 MHz

36 MHz

6 MHz

1 MHz

aaa-011386

-40

-10

110

temperature (°C)

IDD

(mA)

72 MHz

48 MHz

36 MHz

24 MHz

12 MHz

6 MHz

1 MHz

60 MHz

LPC1547JBD48 Datasheet(PDF) 60 Page - NXP Semiconductors

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