HM5259165B datasheet(17/63 Pages) ELPIDA

17 / 63 page

HM5259165B/HM5259805B/HM5259405B-75/A6

Data Sheet E0118H10

From PRECHARGE state, command operation

To [DESL], [NOP]: When these commands are executed, the SDRAM enters the IDLE state after t

RP has

elapsed from the completion of precharge.

From IDLE state, command operation

To [DESL], [NOP], [PRE] or [PALL]: These commands result in no operation.

To [ACTV]: The bank specified by the address pins and the ROW address is activated.

To [REF], [SELF]: The SDRAM enters refresh mode (auto-refresh or self-refresh).

To [MRS]: The synchronous DRAM enters the mode register set cycle.

From ROW ACTIVE state, command operation

To [DESL], [NOP]: These commands result in no operation.

To [READ], [READ A]: A read operation starts. (However, an interval of t

RCD is required.)

To [WRIT], [WRIT A]: A write operation starts. (However, an interval of t

RCD is required.)

To [ACTV]: This command makes the other bank active. (However, an interval of t

RRD is required.)

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands set the SDRAM to precharge mode. (However, an interval of t

RAS is

required.)

From READ state, command operation

To [DESL], [NOP]: These commands continue read operations until the burst operation is completed.

To [READ], [READ A]: Data output by the previous read command continues to be output. After

CAS

latency, the data output resulting from the next command will start.

To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle.

To [ACTV]: This command makes other banks bank active. (However, an interval of t

RRD is required.)

Attempting to make the currently active bank active results in an illegal command.

To [PRE], [PALL]: These commands stop a burst read, and the SDRAM enters precharge mode.

HM5259165B Datasheet(PDF) 17 Page - Elpida Memory