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HM5259165B Datasheet(PDF) 20 Page - Elpida Memory |
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HM5259165B Datasheet(HTML) 20 Page - Elpida Memory |
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20 / 63 page  HM5259165B/HM5259805B/HM5259405B-75/A6 Data Sheet E0118H10 20 Mode Register Configuration The mode register is set by the input to the address pins (A0 to A12, BA0 and BA1) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. BA1, BA0, A11, A10, A12, A9, A8: (OPCODE): The SDRAM has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and burst write: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and single write: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. If this pin is high, the vender test mode is set. A6, A5, A4: (LMODE): These pins specify the CAS latency. A3: (BT): A burst type is specified. A2, A1, A0: (BL): These pins specify the burst length. A2 A1 A0 Burst length 00 0 1 00 1 2 01 0 4 01 1 8 11 1 BT=0 BT=1 10 0 R 11 0 R R 1 2 4 8 R R R A3 0 Sequential 1 Interleave Burst type A6 A5 A4 CAS latency 00 0 R 00 1 R 01 0 2 01 1 3 1XX R A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 OPCODE 0 LMODE BT BL A9 0 0R Write mode A8 0 1 Burst read and burst write 1 Burst read and single write 0 1R 1 10 1 R R R is Reserved (inhibit) X: 0 or 1 A11 A10 A10 X X X A11 X X X 00 A12 BA0 BA1 BA1 BA0 X X X 0 X X X 0 A12 X X X 0 |
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