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PM0059 Datasheet(PDF) 12 Page - STMicroelectronics |
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PM0059 Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 29 page ![]() Flash memory interface PM0059 12/29 DocID15687 Rev 5 2.5.2 Program/erase parallelism The Parallelism size is configured through the PSIZE field in the FLASH_CR register. It represents the number of bytes to be programmed each time a write operation occurs to the Flash memory. PSIZE is limited by the supply voltage and by whether the external VPP supply is used or not. It must therefore be correctly configured in the FLASH_CR register before any programming/erasing operation. A Flash memory erase operation can only be performed by sectors, bank or for the whole Flash memory (mass erase). The erase time depends on PSIZE programmed value. For more details on the erase time, refer to the electrical characteristics section of the device datasheet. Note: Any program or erase operation started with inconsistent program parallelism/voltage range settings may lead to unpredicted results. Even if a subsequent read operation indicates that the logical value was effectively written to the memory, this value may not be retained. To use VPP, an external high-voltage supply (between 8 and 9 V) must be applied to the VPP pad. The external supply must be able to sustain this voltage range even if the DC consumption exceeds 10 mA. It is advised to limit the use of VPP to initial programming on the factory line. The VPP supply must not be applied for more than an hour, otherwise the Flash memory might be damaged. 2.5.3 Erase The Flash memory erase operation can be performed at sector level or on the whole Flash memory (Mass Erase). Mass Erase does not affect the OTP sector or the configuration sector. Sector Erase To erase a sector, follow the procedure below: 1. Check that no Flash memory operation is ongoing by checking the BSY bit in the FLASH_SR register 2. Set the SER bit and select the sector (out of the 12 sectors in the main memory block) you wish to erase (SNB) in the FLASH_CR register 3. Set the STRT bit in the FLASH_CR register 4. Wait for the BSY bit to be cleared Table 4. Program/erase parallelism Voltage range 2.7 - 3.6 V with External VPP Voltage range 2.7 - 3.6 V Voltage range 2.4 - 2.7 V Voltage range 2.1 - 2.4 V Voltage range 1.8 V - 2.1 V(1) 1. If IRROFF is set to VDD on STM32F20xx devices, this value can be lowered to 1.65 V when the device operates in a reduced temperature range. Parallelism size x64 x32 x16 x8 PSIZE(1:0) 11 10 01 00 |
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