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PM0059 Datasheet(PDF) 27 Page - STMicroelectronics |
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PM0059 Datasheet(HTML) 27 Page - STMicroelectronics |
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27 / 29 page ![]() DocID15687 Rev 5 27/29 PM0059 Revision history 28 3 Revision history Table 11. Document revision history Date Revision Changes 24-Jun-2010 1 Updated memory organization in Section 2.3: Flash memory, and replace user-specific block by OTP area. Updated addresses in Table 6: Option byte organization. Definition of BOR_LEV[3:2] bits updated in Table 7: Description of the option bytes and Section 2.8.6: Flash option control register (FLASH_OPTCR) . Modified FLASH_OPTCR reset value in Section 2.8.6: Flash option control register (FLASH_OPTCR) and Table 10: Flash register map and reset values . Updated OPTLOCK definition. Updated definition of ERRIE bit in Section 2.8.5: Flash control register (FLASH_CR) . 09-Dec-2010 2 Updated size of OTP area, and option byte base address and size in Table 2: Flash module organization . Changed 1.62 to 2.1 V range to 1.8 to 2.1 V, added Note 1 as well as wait states 4 to 7 in TTable 3: Number of wait states according to CPU clock (HCLK) frequency . Updated Table 4: Program/erase parallelism. Updated BOR_LEVEL description in Table 7: Description of the option bytes . Renamed FLASH_FOCR, FLASH_OPTCR in Section 2.6.2: Programming user option bytes . Updated Level 1 and Level 2 descriptions in Section 2.6.3: Read protection (RDP). Updated LATENCY bits in Section 2.8.1: Flash access control register (FLASH_ACR) to support up to 7 wait states. Changed access type to bits 0 to 7 to rc-1, and OPERR description in Section 2.8.4: Flash status register (FLASH_SR). Changed access type to bits 16 and 31 to rs in Section 2.8.5: Flash control register (FLASH_CR) . Changed access type to bits 0 and 1 to rs, and added note related to bit 7 to 5 in Section 2.8.6: Flash option control register (FLASH_OPTCR) . 30-Mar-2011 3 Updated OTP area in Section 2.3: Flash memory. Updated Section 2.5: Erase and program operations to mention the fact that read operations cannot be performed during write/erase operations. |
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