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PM0214 Datasheet(PDF) 207 Page - STMicroelectronics |
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PM0214 Datasheet(HTML) 207 Page - STMicroelectronics |
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207 / 245 page  DocID022708 Rev 4 207/245 PM0214 Core peripherals 244 4.4.1 Auxiliary control register (ACTLR) Address offset: 0x00 (base adress = 0xE000 E008) Reset value: 0x0000 0000 Required privilege: Privileged By default this register is set to provide optimum performance from the Cortex-M4 processor, and does not normally require modification. The ACTLR register provides disable bits for the following processor functions: • IT folding • write buffer use for accesses to the default memory map • interruption of multi-cycle instructions. 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 76 54 3 21 0 Reserved DISOO FP DISFP CA DISFOL D DISDE FWBUF DISMC YCINT rw rw rw rw rw Bits 31:10 Reserved Bit 9 DISOOFP Disables floating point instructions completing out of order with respect to integer instructions. Bit 8 DISFPCA Disables automatic update of CONTROL.FPCA. The value of this bit should be written as zero or preserved (SBZP). Bit 7:3 Reserved |
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