PM0214 datasheet(50/245 Pages) STMICROELECTRONICS

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The STM32 Cortex-M4 instruction set

PM0214

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DocID022708 Rev 4

AND, ANDS {Rd,} Rn, Op2

Logical AND

N,Z,C

3.5.2 on page 84

ASR, ASRS

Rd, Rm, <Rs|#n>

Arithmetic shift right

N,Z,C

3.5.3 on page 85

label

Branch

—

3.9.5 on page 141

BFC

Rd, #lsb, #width

Bit field clear

—

3.9.1 on page 137

BFI

Rd, Rn, #lsb, #width

Bit field insert

—

3.9.1 on page 137

BIC, BICS

{Rd,} Rn, Op2

Bit clear

N,Z,C

3.5.2 on page 84

BKPT

#imm

Breakpoint

—

3.11.1 on page 170

label

Branch with link

—

3.9.5 on page 141

BLX

Branch indirect with link

—

3.9.5 on page 141

Branch indirect

—

3.9.5 on page 141

CBNZ

Rn, label

Compare and branch if non

zero

—

3.9.6 on page 143

CBZ

Rn, label

Compare and branch if zero

—

3.9.6 on page 143

CLREX

—

Clear exclusive

—

3.4.9 on page 79

CLZ

Rd, Rm

Count leading zeros

—

3.5.4 on page 86

CMN

Rn, Op2

Compare negative

N,Z,C,V 3.5.5 on page 87

CMP

Rn, Op2

Compare

N,Z,C,V 3.5.5 on page 87

CPSID

iflags

Change processor state,

disable interrupts

—

3.11.2 on page 171

CPSIE

iflags

Change processor state,

enable interrupts

—

3.11.2 on page 171

DMB

—

Data memory barrier

—

3.11.4 on page 172

DSB

—

Data synchronization barrier

—

3.11.4 on page 172

EOR, EORS {Rd,} Rn, Op2

Exclusive OR

N,Z,C

3.5.2 on page 84

ISB

—

Instruction synchronization

barrier

—

3.11.5 on page 173

—

If-then condition block

—

3.9.7 on page 144

LDM

Rn{!}, reglist

Load multiple registers,

increment after

—

3.4.6 on page 75

LDMDB,

LDMEA

Rn{!}, reglist

Load multiple registers,

decrement before

—

3.4.6 on page 75

LDMFD,

LDMIA

Rn{!}, reglist

Load multiple registers,

increment after

—

3.4.6 on page 75

LDR

Rt, [Rn, #offset]

Load register with word

—

3.4 on page 68

LDRB,

LDRBT

Rt, [Rn, #offset]

Load register with byte

—

3.4 on page 68

LDRD

Rt, Rt2, [Rn, #offset]

Load register with two bytes

—

3.4.2 on page 70

LDREX

Rt, [Rn, #offset]

Load register exclusive

—

3.4.8 on page 78

Table 21. Cortex-M4 instructions (continued)

Mnemonic

Operands

Brief description

Flags

Page

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