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TPL0102-100QPWREP Datasheet(PDF) 9 Page - Texas Instruments

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Part # TPL0102-100QPWREP
Description  TPL0102-EP 256-Taps Dual-Channel Digital Potentiometer With Non-Volatile Memory
PDF  36 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TPL0102-100QPWREP Datasheet(HTML) 9 Page - Texas Instruments

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TPL0102-EP
www.ti.com
SLIS149 – JUNE 2014
7.7 Timing Requirements
VDD = 2.7 to 5.5 V, VSS = 0 V, VH = VDD, VL = GND, TJ = –40°C to 125°C (unless otherwise noted). Typical values are at
VDD = 5 V, TJ = 25°C (unless otherwise noted).
STANDARD MODE I2C BUS
FAST MODE I2C BUS
UNIT
MIN
MAX
MIN
MAX
I2C INTERFACE TIMING REQUIREMENTS
ƒSCL
I2C clock frequency
0
100
0
400
kHz
tSCH
I2C clock high time
4
0.6
µs
tSCL
I2C clock low time
4.7
1.3
µs
tsp
I2C spike time
0
50
0
50
ns
tSDS
I2C serial data setup time
250
100
ns
tSDH
I2C serial data hold time
0
0
ns
tICR
I2C input rise time
1000
20 + 0.1Cb
(1)
300
ns
tICF
I2C input fall time
300
20 + 0.1Cb
(1)
300
ns
tICF
I2C output fall time, 10- to 400-pF bus
300
20 + 0.1Cb
(1)
300
ns
tBUF
I2C bus free time between stop and start
4.7
1.3
µs
tSTS
I2C start or repeater start conditions setup time
4.7
1.3
µs
tSTH
I2C start or repeater start condition hold time
4
0.6
µs
tSPS
I2C stop condition setup time
4
0.6
µs
tVD(DATA)
Valid data time, SCL low to SDA output valid
1
1
µs
tVD(DATA)
Valid data time of ACK condition, ACK signal from
1
1
µs
SCL low to SDA (out) low
(1)
Cb = total capacitance of one bus line in pF
Copyright © 2014, Texas Instruments Incorporated
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