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AS4LC4M16S0 Datasheet(PDF) 16 Page - Alliance Semiconductor Corporation

Part # AS4LC4M16S0
Description  3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM
PDF  24 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS4LC4M16S0 Datasheet(HTML) 16 Page - Alliance Semiconductor Corporation

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ALLIANCE SEMICONDUCTOR
7/5/00
AS4LC4M16S0
AS4LC16M4S0
write interrupted by write (BL = 4)
tCCD = CAS to CAS delay (= 1 CLK)
tCDL = last address in to new column addres delay (= 1 CLK)
write interrupted by read (CL = 2, BL = 4)
tCCD = CAS to CAS delay (= 1 CLK)
tCDL = last address in to new column addres delay (= 1 CLK)
read interrupted by write (CL = 3, BL = 4)
* To prevent bus contention, maintain a gap between data in and data out.
Burst termination
Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted
during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is
asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously.
Burst stop command waveform, read cycle
(BL = 8)
CLK
CMD
ADD
DQ
DA0
DB0
DB1
DB2
DB3
A0
B0
Write data
Write data
tCCD
tCDL
tCDL
CLK
CMD
ADD
DQ (CL2)
DQ (CL3)
Write data
Read data
AB
DA0
QB0
QB1
QB2
QB3
DA0
QB0
QB1
QB2
QB3
tCCD
CLK
CMD
DQM
DQ
Read data
Write data*
D0
D1
D2
D3
Q0
CLK
CMD
DQ (CL = 2)
DQ (CL = 3)
Read data
Burst stop
Read data
Q0
Q1
Q2
Q0
Q1
Q2



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