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AS4LC4M16S0 Datasheet(PDF) 1 Page - Alliance Semiconductor Corporation |
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AS4LC4M16S0 Datasheet(HTML) 1 Page - Alliance Semiconductor Corporation |
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1 / 24 page  Advance information Copyright ©2000 Alliance Semiconductor. All rights reserved. ® AS4LC8M8S0 AS4LC4M16S0 7/5/00 ALLIANCE SEMICONDUCTOR 1 3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM Features • PC100/133 compliant • Organization - 2,097,152 words × 8 bits × 4 banks (8M×8) - 1,048,576 words × 16 bits × 4 banks (4M×16) • Fully synchronous - All signals referenced to positive edge of clock • Four internal banks controlled by BA0/BA1 (bank select) •High speed - 133/125/100 MHz - 5.4 ns (133 MHz)/6 ns (125/100 MHz) clock access time • Low power consumption - Standby: 7.2 mW max, CMOS I/O • 4096 refresh cycles, 64 ms refresh interval • Auto refresh and self refresh • Automatic and direct precharge • Burst read, single write operation • Can assert random column address in every cycle • LVTTL compatible I/O • 3.3V power supply • JEDEC standard package, pinout and function - 400 mil, 54-pin TSOP II • Read/write data masking • Programmable burst length (1/2/4/8/full page) • Programmable burst sequence (sequential/interleaved) • Programmable CAS latency (2/3) Pin arrangement A3 VCC A4 VSS VCC DQ0 VCCQ DQ1 DQ2 VSSQ DQ3 DQ4 VCCQ DQ5 DQ6 VSSQ DQ7 VCC LDQM VSS DQ15 VSSQ DQ14 DQ13 VCCQ DQ12 DQ11 VSSQ DQ10 DQ9 VCCQ DQ8 VSS NC UDQM CLK CKE 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 32 31 30 WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 NC A11 A9 A8 A7 A6 A5 26 27 29 28 NC DQ1 NC DQ2 NC DQ3 NC NC DQ7 NC DQ6 NC DQ5 NC DQ4 NC DQM A3 VCC VCC DQ0 VCCQ VSSQ VCCQ VSSQ VCC WE CAS RAS CS BA0 BA1 A10 A0 A1 A2 A4 VSS VSS VSSQ VCCQ VSSQ VCCQ VSS NC CLK CKE NC A11 A9 A8 A7 A6 A5 AS4LC4M16S0 AS4LC4M16S0 Pin designation Pin(s) Description DQM (8M×8) UDQM/LDQM (4M×16) Output disable/write mask A0 to A11 Address inputs BA0, BA1 Bank select inputs DQ0 to DQ7 (8M×8) DQ0 to DQ15 (4M×16) Input/output RAS Row address strobe CAS Column address strobe WE Write enable CS Chip select VCC, VCCQ Power (3.3V ± 0.3V) VSS, VSSQ Ground CLK Clock input CKE Clock enable Selection guide Symbol -75 (PC133) -8 -10F (PC100) -10 (PC100) Unit Bus frequency fmax 133 125 100 100 MHz Minimum clock access time CL = 2 tAC –– 6– ns CL = 3 tAC 5.4 6 – 6 ns Minimum setup time tS 1.5 2 2 2 ns Minimum hold time tH 0.81.0 1.01.0 ns Minimum RAS to CAS delay tRCD 3323 cycles Minimum RAS precharge time tRP 3323 cycles Remarks: (CL/tRCD/tRP) 3/3/3 3/3/3 2/2/2 3/3/3 |
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