| Electronic Components Datasheet Search |
|
AS4LC4M16S0 Datasheet(PDF) 4 Page - Alliance Semiconductor Corporation |
|
|
|||||||||||||||||||||||||||||
AS4LC4M16S0 Datasheet(HTML) 4 Page - Alliance Semiconductor Corporation |
|
4 / 24 page ![]() ® 4 ALLIANCE SEMICONDUCTOR 7/5/00 AS4LC4M16S0 AS4LC16M4S0 Commands 1 OP = operation code. A0~A11 and BA0~BA1 program keys. 2 MRS can be issued only when all banks are precharged. A new command can be issued 1 clock cycle after MRS. 3 Auto refresh functions similarly to CBR DRAM refresh. However, precharge is automatic. Auto/self refresh can only be issued after all banks are precharged. 4 BA0~BA1: bank select addresses. If A10/AP is High at row precharge, BA0 and BA1 are ignored and all banks are selected. During read, write, row active, and prechage: If BA0 and BA1 are Low, Bank A is selected. If BA0 = Low and BA1 = High, Bank B is selected. If BA0 = High and BA1 = Low, Bank C is selected. If BA0 and BA1 are High, Bank D is selected. 5 A new read/write command to the same bank cannot be issued during a burst read/write with auto precharge. A new row active command can be issued after t(t RP/tCK + BL +) cycles. 6 Burst stop command valid at every burst length. 7 DQM sampled at positive edge of CLK. Data-in may be masked at every CLK (Write DQM latency is 0). Data-out mask is active 2 CLK cycles after issuance. (Read DQM latency is 2). Command CKEn-1 CKEn CS RAS CAS WE DQM BA0/ BA1 A10 A9–A0 DQ Note Register Mode register set H* HL L L L X Op code X 1,2 Refresh Auto refresh H H L L L H X – X – X 3 Self refresh Entry H L L L L H X – – 3 Exit L H LH H H X – – 3 H XXX X – – 3 Bank activate H H L L H H X V row address X Read Auto precharge disable HH L H L H X V L column address X 4 Auto precharge enable H 4,5 Write Auto precharge disable HH L H L L X V L column address Valid 4 Auto precharge enable H 4,5 Burst stop H H L H H L X X Active 6 Precharge Selected bank HH L L H L X VL XX 4 All banks X H Clock suspend or active power down Entry H L H XXX XX X X X L VVV Exit L H X XXX Precharge power down mode Entry H L H XXX XX X X X LH H H Exit L H H XXX L VVV DQM Write enable/output enable HH X XXX H XX X X 7 Write inhibit/Output High-Z No operation command H X H XXX X XX X X LH H H X |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |