REF LEVEL

0.000 dB

0.0 deg

100

1k

START 100.000 Hz

10k

STOP 100 000.000 Hz

/DIV

10.000 dB

45.000 deg

100k

GAIN

PHASE

0

REF LEVEL

0.000 dB

0.0 deg

100

1k

START 100.000 Hz

10k

STOP 100 000.000 Hz

/DIV

10.000 dB

45.000 deg

100k

GAIN

PHASE

0

LM5574-Q1

www.ti.com

SNOSB22C – OCTOBER 2008 – REVISED OCTOBER 2014

Typical Application (continued)

Figure 18. Gain and Phase of Modulator

Components R4 and C5 configure the error amplifier as a type II configuration which has a pole at DC and a

the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a very stable

loop with 90 degrees of phase margin.

For the design example, a target loop bandwidth (crossover frequency) of 25kHz was selected. The

frequency. This constrains the product of R4 and C5 for a desired compensation network zero 1 / (2

π R4 C5) to

be less than 2kHz. Increasing R4, while proportionally decreasing C5, increases the error amp gain. Conversely,

decreasing R4 while proportionally increasing C5, decreases the error amp gain. For the design example C5 was

selected for 0.022µF and R4 was selected for 24.9k

Ω. These values configure the compensation network zero at

Figure 19. Error Amplifier Gain and Phase

The overall loop can be predicted as the sum (in dB) of the modulator gain and the error amp gain.

Copyright © 2008–2014, Texas Instruments Incorporated

Submit Documentation Feedback

21

Product Folder Links: LM5574-Q1