SYNC

10k

S

R

Q

Q

DEADTIME

ONE-SHOT

5V

2.5V

I = f(RT)

SYNC

LM5574

UP TO 5 TOTAL

DEVICES

LM5574

SYNC

SYNC

AGND

LM5574

SW

CLK

SYNC

SW

500 ns

LM5574-Q1

SNOSB22C – OCTOBER 2008 – REVISED OCTOBER 2014

www.ti.com

Device Functional Modes (continued)

Figure 9. Sync from External Clock

Figure 10. Sync from Multiple Devices

Multiple LM5574-Q1 devices can be synchronized together simply by connecting the SYNC pins together. In this

configuration, all of the devices will be synchronized to the highest frequency device. The diagram in Figure 11

illustrates the SYNC input/output features of the LM5574-Q1. The internal oscillator circuit drives the SYNC pin

with a strong pull-down / weak pull-up inverter. When the SYNC pin is pulled low either by the internal oscillator

or an external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the

SYNC pins of several LM5574-Q1 IC’s are connected together, the IC with the highest internal clock frequency

will pull the connected SYNC pins low first and terminate the oscillator ramp cycles of the other IC’s. The

LM5574-Q1 with the highest programmed clock frequency will serve as the master and control the switching

frequency of the all the devices with lower oscillator frequency.

Figure 11. Simplified Oscillator Block Diagram and SYNC I/O Circuit

7.4.3 Error Amplifier and PWM Comparator

The internal high gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference (1.225 V). The output of the error amplifier is

connected to the COMP pin allowing the user to provide loop compensation components, generally a type II

network, as illustrated in Figure 16. This network creates a pole at DC, a zero and a noise reducing high

frequency pole. The PWM comparator compares the emulated current sense signal from the RAMP generator to

the error amplifier output voltage at the COMP pin.

12

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