TMS320DM814X datasheet(160/376 Pages) TI1

160 / 376 page

TMS320DM8148, TMS320DM8147

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

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Some peripheral pin functions can be routed to more than one device pin. These types of peripheral pin

functions are called Multimuxed (MM) and may have different Switching Characteristics and Timing

Requirements for each device pin option. The Multimuxed peripheral pin functions are labeled as "MM" in

Terminal Functions tables in Section 3.2, Terminal Functions and the associated timings for each MM pin

option are in Section 8, Peripheral Information and Timings.

For more detailed information on the Pin Control 1 through Pin Control 270 (PINCNTLx) registers

breakout, see Figure 4-1 and Table 4-11. For the register reset values of each PINCNTLx register, see

Table 4-13, PINCNTLx Registers MUXMODE Functions.

Figure 4-1. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Breakout

RESERVED

RSV

RXAC

PLLTY

PLLU

TIVE

PESE

DEN

R - 0000 0000

R - 0000

R/W (see Table 4-13 for register

reset value)

RESERVED

MUXMODE[7:0] (see Table 4-13)

R - 0000 0000

R/W - 0000 0000

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 4-11. PINCNTL1 – PINCNTL270 (PINCNTLx) Registers Bit Descriptions

Bit

Field

Description

Comments

31:20

RESERVED

Reserved. Read only, writes have no effect.

Reserved. This bit must always be written with the

RSV

reset (default) value.

(See Table 4-13 for full register reset value)

Receiver Enable

RXACTIVE

0 = Receiver Disabled

1 = Receiver Enabled

For PINCNTLx register reset value

Pullup/Pulldown Type Selection bit

examples, see Table 4-12,

PLLTYPSEL

PNICNTLx Register Reset Value

0 = Pulldown (PD) selected

Examples.

1 = Pullup (PU) selected

For the full register reset values of all

Pullup/Pulldown Enable bit

PINCNTLx registers, see Table 4-13,

PLLUDEN

0 = PU/PD enabled

PINCNTLx Registers MUXMODE

1 = PU/PD disabled

Functions.

15:8

RESERVED

Reserved. Read only, writes have no effect.

MUXMODE Selection bits

These bits select the multiplexed mode pin function

settings (seeTable 4-13, PINCNTLx Registers

7:0

MUXMODE[7:0]

MUXMODE Functions). A value of zero results in the

pin being tri-stated. Non-zero values other than those

shown in Table 4-13 are Reserved.

160

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