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TMS320DM814x Datasheet(PDF) 225 Page - Texas Instruments

Part # TMS320DM814x
Description  DaVinci Video Processors
PDF  376 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
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TMS320DM814x Datasheet(HTML) 225 Page - Texas Instruments

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TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
8.4
EDMA
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the device. These data transfers include cache servicing, non-cacheable memory accesses, user-
programmed data transfers, and host accesses.
8.4.1
EDMA Channel Synchronization Events
The EDMA Channel controller supports up to 64 channels that service peripherals and memory. Each
EDMA channel is mapped to a defaul EDMA synchronization event as shown in Table 8-3. By default,
each event uses the parameter entry that matches its event number. However, because the device
includes a channel mapping feature, each event may be mapped to any of 512 parameter table entries.
For more detailed information, see the Enhanced Direct Memory Access Controller chapter of the
TMS320DM814x DaVinci Digital Media Processors Technical Reference Manual (Literature Number:
SPRUGZ8).
Table 8-3. EDMA Default Synchronization Events
EVENT
DEFAULT
DEFAULT EVENT DESCRIPTION
NUMBER
EVENT NAME
0-1
–
Reserved
2
SDTXEVT1
SD1 Transmit
3
SDRXEVT1
SD1 Receive
4-7
–
Reserved
8
AXEVT0
McASP0 Transmit
9
AREVT0
McASP0 Receive
10
AXEVT1
McASP1 Transmit
11
AREVT1
McASP1 Receive
12
AXEVT2
McASP2 Transmit
13
AREVT2
McASP2 Receive
14
BXEVT
McBSP Transmit
15
BREVT
McBSP Receive
16
SPI0XEVT0
SPI0 Transmit 0
17
SPI0REVT0
SPI0 Receive 0
18
SPI0XEVT1
SPI0 Transmit 1
19
SPI0REVT1
SPI0 Receive 1
20
SPI0XEVT2
SPI0 Transmit 2
21
SPI0REVT2
SPI0 Receive 2
22
SPI0XEVT3
SPI0 Transmit 3
23
SPI0REVT3
SPI0 Receive 3
24
SDTXEVT0
SD0 Transmit
25
SDRXEVT0
SD0 Receive
26
UTXEVT0
UART0 Transmit
27
URXEVT0
UART0 Receive
28
UTXEVT1
UART1 Transmit
29
URXEVT1
UART1 Receive
30
UTXEVT2
UART2 Transmit
31
URXEVT2
UART2 Receive
32-35
–
Reserved
36
ISS_DMA_REQ1
ISS Event 1
37
ISS_DMA_REQ2
ISS Event 2
38
ISS_DMA_REQ3
ISS Event 3
39
ISS_DMA_REQ4
ISS Event 4
Copyright © 2011–2013, Texas Instruments Incorporated
Peripheral Information and Timings
225
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Product Folder Links: TMS320DM8148 TMS320DM8147



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