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TMS320DM814x Datasheet(PDF) 288 Page - Texas Instruments |
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TMS320DM814x Datasheet(HTML) 288 Page - Texas Instruments |
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288 / 376 page  TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com 8.13.1 DDR2/3 Memory Controller Register Descriptions Table 8-50. DDR2/3 Memory Controller Registers DDR0 HEX ADDRESS DDR1 HEX ADDRESS ACRONYM REGISTER NAME 0x4C00 0004 0x4D00 0004 SDRSTAT SDRAM Status Register 0x4C00 0008 0x4D00 0008 SDRCR SDRAM Configuration Register 0x4C00 000C 0x4D00 000C SDRCR2 SDRAM Configuration Register 2 0x4C00 0010 0x4D00 0010 SDRRCR SDRAM Refresh Control Register 0x4C00 0014 0x4D00 0014 SDRRCSR SDRAM Refresh Control Shadow Register 0x4C00 0018 0x4D00 0018 SDRTIM1 SDRAM Timing 1 Register 0x4C00 001C 0x4D00 001C SDRTIM1SR SDRAM Timing 1 Shadow Register 0x4C00 0020 0x4D00 0020 SDRTIM2 SDRAM Timing 2 Register 0x4C00 0024 0x4D00 0024 SDRTIM2SR SDRAM Timing 2 Shadow Register 0x4C00 0028 0x4D00 0028 SDRTIM3 SDRAM Timing 3 Register 0x4C00 002C 0x4D00 002C SDRTIM3SR SDRAM Timing 3 Shadow Register 0x4C00 0038 0x4D00 0038 PMCR Power Management Control Register 0x4C00 003C 0x4D00 003C PMCSR Power Management Control Shadow Register 0x4C00 0054 0x4D00 0054 PBBPR Peripheral Bus Burst Priority Register 0x4C00 00A0 0x4D00 00A0 EOI End of Interrupt Register 0x4C00 00A4 0x4D00 00A4 SOIRSR System OCP Interrupt Raw Status Register 0x4C00 00AC 0x4D00 00AC SOISR System OCP Interrupt Status Register 0x4C00 00B4 0x4D00 00B4 SOIESR System OCP Interrupt Enable Set Register 0x4C00 00BC 0x4D00 00BC SOIECR System OCP Interrupt Enable Clear Register 0x4C00 00C8 0x4D00 00C8 ZQCR SDRAM Output Impedance Calibration Configuration Register 0x4C00 00D4 0x4D00 00D4 RDWR_LVL_RMP_WIN Read-Write Leveling Ramp Window Register 0x4C00 00D8 0x4D00 00D8 RDWR_LVL_RMP_CTRL Read-Write Leveling Ramp Control Register 0x4C00 00DC 0x4D00 00DC RWLCR Read-Write Leveling Control Register 0x4C00 00E4 0x4D00 00E4 DDRPHYCR DDR PHY Control Register 0x4C00 00E8 0x4D00 00E8 DDRPHYCSR DDR PHY Control Shadow Register 0x4C00 0100 0x4D00 0100 PRI_COS_MAP Priority to Class of Service Mapping Register 0x4C00 0104 0x4D00 0104 CONNID_COS_1_MAP Connection ID to Class of Service 1 Mapping Register 0x4C00 0108 0x4D00 0108 CONNID_COS_2_MAP Connection ID to Class of Service 2 Mapping Register 0x4C00 0120 0x4D00 0120 RD_WR_EXEC_THRSH Read Write Execution Threshold Register 8.13.2 DDR2/DDR3 PHY Register Descriptions Table 8-51. DDR2/DDR3 PHY Registers DDR0 HEX DDR1 HEX ACRONYM REGISTER NAME ADDRESS ADDRESS 0x47C0_C41C 0x47C0_C81C CMD0_REG_PHY_CTRL_SLAVE_RATIO_0 DDR PHY Command 0 Address/Command Slave Ratio Register 0x47C0_C428 0x47C0_C828 CMD0_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Command 0 Address/Command DLL Lock Difference Register 0x47C0_C42C 0x47C0_C82C CMD0_REG_PHY_INVERT_CLKOUT_0 DDR PHY Command 0 Invert Clockout Selection Register 0x47C0_C450 0x47C0_C850 CMD1_REG_PHY_CTRL_SLAVE_RATIO_0 DDR PHY Command 1 Address/Command Slave Ratio Register 0x47C0_C45C 0x47C0_C85C CMD1_REG_PHY_DLL_LOCK_DIFF_0 DDR PHY Command 1 Address/Command DLL Lock Difference Register 288 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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