TMS320DM814X datasheet(302/376 Pages) TI1

302 / 376 page

TMS320DM8148, TMS320DM8147

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

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Table 8-64. DQS and DQ Routing Specification

NO.

PARAMETER

MIN

TYP

MAX

UNIT

Center-to-center DQS-DQSn spacing in E0|E1|E2|E3

DQS-DQSn skew in E0|E1|E2|E3

Mils

Center-to-center DQS to other DDR2 trace spacing(1)

DQS/DQ nominal trace length (2)(3)(4)

DQLM-50

DQLM

DQLM+50

Mils

DQ-to-DQS skew length mismatch(2)(3)(4)

100

Mils

DQ-to-DQ skew length mismatch(2)(3)(4)

100

Mils

DQ-to-DQ/DQS via count mismatch(2)(3)(4)

Vias

Center-to-center DQ to other DDR2 trace spacing(1)(5)

Center-to-center DQ to other DQ trace spacing(1)(6)(7)

DQ/DQS E skew length mismatch(2)(3)(4)

100

Mils

(1)

Center-to-center spacing is allowed to fall to minimum (w) for up to 500 mils of routed length to accommodate BGA escape and routing

congestion.

(2)

A 16-bit DDR memory system has two sets of data net classes; one for data byte 0, and one for data byte 1, each with an associated

DQS (2 DQSs) per DDR EMIF used.

(3)

A 32-bit DDR memory system has four sets of data net classes; one each for data bytes 0 through 3, and each associated with a DQS

(4 DQSs) per DDR EMIF used.

(4)

There is no need, and it is not recommended, to skew match across data bytes; that is, from DQS0 and data byte 0 to DQS1 and data

byte 1.

(5)

DQs from other DQS domains are considered other DDR2 trace.

(6)

DQs from other data bytes are considered other DDR2 trace.

(7)

DQLM is the longest Manhattan distance of each of the DQS and DQ net classes.

8.13.4.2 DDR3 Routing Specifications

8.13.4.2.1 DDR3 versus DDR2

This specification only covers PCB designs that utilize DDR3 memory. PCB designs using other types of

DDR memory should follow the specification appropriate for that type of memory. It is currently not

possible to design a single PCB that supports multiple types of DDR memory.

8.13.4.2.2 DDR3 EMIFs

A processor may contain more than one EMIF. This specification covers only one EMIF and needs to be

implemented for each additional EMIF. Requirements are identical between the EMIFs, however, the PCB

layouts will most likely be different.

8.13.4.2.3 DDR3 Device Combinations

Since there are several possible combinations of device counts and single- or dual-side mounting,

Table 8-65 summarizes the supported device configurations.

Table 8-65. Supported DDR3 Device Combinations(1)

NUMBER OF DDR3 DEVICES

DDR3 DEVICE WIDTH (BITS)

MIRRORED?

DDR3 EMIF WIDTH (BITS)

Y(2)

Y(3)

(1)

This table is per EMIF.

(2)

Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of

the board.

(3)

This is two mirrored pairs of DDR3 devices.

302

Peripheral Information and Timings

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