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TMS320DM814x Datasheet(PDF) 338 Page - Texas Instruments |
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TMS320DM814x Datasheet(HTML) 338 Page - Texas Instruments |
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338 / 376 page  START XMIT Valid Valid Valid END 7 SDx_CLK SDx_CMD 13 10 9 13 13 13 TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com Table 8-85. MMC/SD/SDIO Registers(1) (continued) MMC/SD/SDIO0 MMC/SD/SDIO1 MMC/SD/SDIO2 ACRONYM REGISTER NAME HEX ADDRESS HEX ADDRESS HEX ADDRESS 0x4806 0250 0x481D 8250 0x4781 0250 MMCHS_FE Force Event 0x4806 0254 0x481D 8254 0x4781 0254 MMCHS_ADMAES ADMA Error Status 0x4806 0258 0x481D 8258 0x4781 0258 MMCHS_ADMASAL ADMA System address Low bits 0x4806 025C 0x481D 825C 0x4781 025C MMCHS_ADMASAH ADMA System address High bits 0x4806 02FC 0x481D 82FC 0x4781 02FC MMCHS_REV Versions 8.16.2 MMC/SD/SDIO Electrical Data/Timing Table 8-86. Timing Requirements for MMC/SD/SDIO (see Figure 8-86, Figure 8-88) OPP100/120/166 NO ALL MODES UNIT . MIN MAX 1 tsu(CMDV-CLKH) Setup time, SD_CMD valid before SD_CLK rising clock edge 4.1 ns SD1 1.9 2 th(CLKH-CMDV) Hold time, SD_CMD valid after SD_CLK rising clock edge ns SD0, SD2 2.9 3 tsu(DATV-CLKH) Setup time, SD_DATx valid before SD_CLK rising clock edge 4.1 ns SD1 1.9 4 th(CLKH-DATV) Hold time, SD_DATx valid after SD_CLK rising clock edge ns SD0, SD2 2.9 Table 8-87. Switching Characteristics Over Recommended Operating Conditions for MMC/SD/SDIO (see Figure 8-85 through Figure 8-88) OPP100/120/166 MODES NO. PARAMETER UNIT 3.3 V STD 3.3 V HS 1.8 V SDR12 1.8 V SDR25 MIN MAX MIN MAX fop(CLK) Operating frequency, SD_CLK 24 48 MHz 7 tc(CLK) Operating period: SD_CLK 41.7 20.8 ns fop(CLKID) Identification mode frequency, SD_CLK 400 400 kHz 8 tc(CLKID) Identification mode period: SD_CLK 2500.0 2500.0 ns 9 tw(CLKL) Pulse duration, SD_CLK low 0.5*P(1) 0.5*P(1) ns 10 tw(CLKH) Pulse duration, SD_CLK high 0.5*P(1) 0.5*P(1) ns 11 tr(CLK) Rise time, All Signals (10% to 90%) 2.2 2.2 ns 12 tf(CLK) Fall time, All Signals (10% to 90%) 2.2 2.2 ns Delay time, SD_CLK rising clock edge to SD_CMD 13 td(CLKL-CMD) 1.5 10 1.5 10 ns transition Delay time, SD_CLK rising clock edge to SD_DATx 14 td(CLKL-DAT) 1.5 10 1.5 10 ns transition (1) P = SD_CLK period. Figure 8-85. MMC/SD/SDIO Host Command Timing 338 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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