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TMS320DM814x Datasheet(PDF) 348 Page - Texas Instruments |
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TMS320DM814x Datasheet(HTML) 348 Page - Texas Instruments |
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348 / 376 page  SATA Interface (Processor) SATA Connector SATA_TXN0 SATA_TXP0 SATA_RXN0 SATA_RXP0 TX- TX+ RX- RX+ 10 nF 10 nF 10 nF 10 nF TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com Table 8-99. SATA Registers (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x4A14 012C P0SCTL Port 0 Serial ATA Control (SControl) 0x4A14 0130 P0SERR Port 0 Serial ATA Error (SError) 0x4A14 0134 P0SACT Port 0 Serial ATA Active (SActive) 0x4A14 0138 P0CI Port 0 Command Issue 0x4A14 013C P0SNTF Port 0 Serial ATA Notification 0x4A14 0140 - 0x4A14 016C - Reserved 0x4A14 0170 P0DMACR Port 0 DMA Control 0x4A14 0174 - 0x4A14 017C - Reserved 0x4A14 0180 - 0x4A14 01FC - Reserved 0x4A14 1100 IDLE Idle and Standby Modes 0x4A14 1104 CFGRX0 PHY Configuration Receive 0 Register 0x4A14 1108 CFGRX1 PHY Configuration Receive 1 Register 0x4A14 110C CFGRX2 PHY Configuration Receive 2 Register 0x4A14 1110 CFGRX3 PHY Configuration Receive 3 Register 0x4A14 1114 CFGRX4 PHY Configuration Receive 4 Register 0x4A14 1118 STSRX Receive Bus PHY-to-Controller Status Register (Used for Debug Purposes) 0x4A14 111C CFGTX0 PHY Configuration Transmit 0 Register 0x4A14 1120 CFGTX1 PHY Configuration Transmit 1 Register 0x4A14 1124 CFGTX2 PHY Configuration Transmit 2 Register 0x4A14 1128 CFGTX3 PHY Configuration Transmit 3 Register 0x4A14 112C CFGTX4 PHY Configuration Transmit 4 Register 0x4A14 1130 STSTX Transmit Bus Controller-to-PHY Status Register (Used for Debug Purposes) 8.18.2 SATA Interface Design Guidelines This section provides PCB design and layout guidelines for the SATA interface. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk, and signal timing. Simulation and system design work has been done to ensure the SATA interface requirements are met. A standard 100-MHz differential clock source must be used for SATA operation (for details, see Section 7.4.2, SERDES_CLKN/P Input Clock). 8.18.2.1 SATA Interface Schematic Figure 8-89 shows the data portion of the SATA interface schematic. The specific pin numbers can be obtained from Table 3-26, Serial ATA Terminal Functions. Figure 8-89. SATA Interface High-Level Schematic 348 Peripheral Information and Timings Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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